Updating timer compare offsets
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parent
598a48b178
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7a2f950667
@ -246,7 +246,7 @@ macro_rules! adc_input {
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// Generate DMA events when an output compare of the timer hits the specified
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// Generate DMA events when an output compare of the timer hits the specified
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// value.
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// value.
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trigger_channel.listen_dma();
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trigger_channel.listen_dma();
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trigger_channel.to_output_compare(2);
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trigger_channel.to_output_compare(2 + $index);
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// The trigger stream constantly writes to the SPI CR1 using a static word
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// The trigger stream constantly writes to the SPI CR1 using a static word
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// (which is a static value to enable the SPI transfer). Thus, neither the
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// (which is a static value to enable the SPI transfer). Thus, neither the
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@ -14,7 +14,7 @@
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///! the DAC without requiring the CPU.
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///! the DAC without requiring the CPU.
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///!
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///!
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///! In order to ensure alignment between the ADC sample batches and DAC output code batches, a DAC
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///! In order to ensure alignment between the ADC sample batches and DAC output code batches, a DAC
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///! output batch is always exactly 2 batches after the ADC batch that generated it.
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///! output batch is always exactly 3 batches after the ADC batch that generated it.
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///!
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///!
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///! The DMA transfer for the DAC output codes utilizes a double-buffer mode to avoid losing any
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///! The DMA transfer for the DAC output codes utilizes a double-buffer mode to avoid losing any
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///! transfer events generated by the timer (for example, when 2 update cycles occur before the DMA
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///! transfer events generated by the timer (for example, when 2 update cycles occur before the DMA
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@ -134,7 +134,7 @@ macro_rules! dac_output {
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// Generate DMA events when an output compare of the timer hitting zero (timer roll over)
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// Generate DMA events when an output compare of the timer hitting zero (timer roll over)
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// occurs.
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// occurs.
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trigger_channel.listen_dma();
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trigger_channel.listen_dma();
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trigger_channel.to_output_compare(0);
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trigger_channel.to_output_compare(4 + $index);
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// The stream constantly writes to the TX FIFO to write new update codes.
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// The stream constantly writes to the TX FIFO to write new update codes.
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let trigger_config = DmaConfig::default()
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let trigger_config = DmaConfig::default()
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