From 7a2f950667ef9de53a114958fb0749990dac91e1 Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Mon, 18 Jan 2021 13:41:23 +0100 Subject: [PATCH] Updating timer compare offsets --- src/adc.rs | 2 +- src/dac.rs | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/adc.rs b/src/adc.rs index 76a42a4..48792d9 100644 --- a/src/adc.rs +++ b/src/adc.rs @@ -246,7 +246,7 @@ macro_rules! adc_input { // Generate DMA events when an output compare of the timer hits the specified // value. trigger_channel.listen_dma(); - trigger_channel.to_output_compare(2); + trigger_channel.to_output_compare(2 + $index); // The trigger stream constantly writes to the SPI CR1 using a static word // (which is a static value to enable the SPI transfer). Thus, neither the diff --git a/src/dac.rs b/src/dac.rs index 971a7de..a22e5da 100644 --- a/src/dac.rs +++ b/src/dac.rs @@ -14,7 +14,7 @@ ///! the DAC without requiring the CPU. ///! ///! In order to ensure alignment between the ADC sample batches and DAC output code batches, a DAC -///! output batch is always exactly 2 batches after the ADC batch that generated it. +///! output batch is always exactly 3 batches after the ADC batch that generated it. ///! ///! The DMA transfer for the DAC output codes utilizes a double-buffer mode to avoid losing any ///! transfer events generated by the timer (for example, when 2 update cycles occur before the DMA @@ -134,7 +134,7 @@ macro_rules! dac_output { // Generate DMA events when an output compare of the timer hitting zero (timer roll over) // occurs. trigger_channel.listen_dma(); - trigger_channel.to_output_compare(0); + trigger_channel.to_output_compare(4 + $index); // The stream constantly writes to the TX FIFO to write new update codes. let trigger_config = DmaConfig::default()