board: dma documentation
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05189fe8d2
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52
src/board.rs
52
src/board.rs
@ -468,30 +468,30 @@ fn dma1_setup(
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dma1.st[0].m0ar.write(|w| unsafe { w.bits(ma as u32) });
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dma1.st[0].ndtr.write(|w| w.ndt().bits(1));
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dmamux1.ccr[0].modify(|_, w| w.dmareq_id().tim2_up());
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dma1.st[0].cr.modify(|_, w| unsafe {
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dma1.st[0].cr.modify(|_, w|
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w.pl()
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.bits(0b01) // medium
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.medium()
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.circ()
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.set_bit() // reload ndtr
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.enabled()
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.msize()
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.bits(0b10) // 32
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.bits32()
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.minc()
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.clear_bit()
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.fixed()
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.mburst()
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.bits(0b00)
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.single()
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.psize()
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.bits(0b10) // 32
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.bits32()
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.pinc()
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.clear_bit()
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.fixed()
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.pburst()
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.bits(0b00)
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.single()
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.dbm()
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.clear_bit()
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.disabled()
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.dir()
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.bits(0b01) // memory_to_peripheral
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.memory_to_peripheral()
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.pfctrl()
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.clear_bit() // dma is FC
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});
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.dma()
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);
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dma1.st[0].fcr.modify(|_, w| w.dmdis().clear_bit());
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dma1.st[0].cr.modify(|_, w| w.en().set_bit());
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@ -502,30 +502,30 @@ fn dma1_setup(
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dma1.st[1].m0ar.write(|w| unsafe { w.bits(ma as u32) });
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dma1.st[1].ndtr.write(|w| w.ndt().bits(1));
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dmamux1.ccr[1].modify(|_, w| w.dmareq_id().tim2_up());
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dma1.st[1].cr.modify(|_, w| unsafe {
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dma1.st[1].cr.modify(|_, w|
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w.pl()
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.bits(0b01) // medium
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.medium()
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.circ()
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.set_bit() // reload ndtr
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.enabled()
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.msize()
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.bits(0b10) // 32
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.bits32()
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.minc()
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.clear_bit()
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.fixed()
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.mburst()
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.bits(0b00)
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.single()
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.psize()
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.bits(0b10) // 32
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.bits32()
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.pinc()
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.clear_bit()
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.fixed()
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.pburst()
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.bits(0b00)
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.single()
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.dbm()
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.clear_bit()
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.disabled()
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.dir()
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.bits(0b01) // memory_to_peripheral
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.memory_to_peripheral()
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.pfctrl()
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.clear_bit() // dma is FC
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});
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.dma()
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);
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dma1.st[1].fcr.modify(|_, w| w.dmdis().clear_bit());
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dma1.st[1].cr.modify(|_, w| w.en().set_bit());
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}
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