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lockin-external: expand output config

master
Robert Jördens 2021-03-02 11:46:19 +01:00
parent 6a96160cd0
commit 733d4243c3
1 changed files with 18 additions and 16 deletions
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34
src/bin/lockin-external.rs
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@ -34,13 +34,13 @@ pub struct Settings {
lockin_harmonic: i32, lockin_harmonic: i32,
lockin_phase: i32, lockin_phase: i32,
output_conf: Conf, output_conf: [Conf; 2],
} }
impl Default for Settings { impl Default for Settings {
fn default() -> Self { fn default() -> Self {
Self { Self {
afe: [AfeGain::G1, AfeGain::G1], afe: [AfeGain::G1; 2],
pll_tc: [21, 21], // frequency and phase settling time (log2 counter cycles) pll_tc: [21, 21], // frequency and phase settling time (log2 counter cycles)
@ -48,7 +48,7 @@ impl Default for Settings {
lockin_harmonic: -1, // Harmonic index of the LO: -1 to _de_modulate the fundamental (complex conjugate) lockin_harmonic: -1, // Harmonic index of the LO: -1 to _de_modulate the fundamental (complex conjugate)
lockin_phase: 0, // Demodulation LO phase offset lockin_phase: 0, // Demodulation LO phase offset
output_conf: Conf::Quadrature, output_conf: [Conf::Quadrature; 2],
} }
} }
} }
@ -150,14 +150,10 @@ const APP: () = {
let lockin = c.resources.lockin; let lockin = c.resources.lockin;
let settings = c.resources.settings; let settings = c.resources.settings;
let timestamp = c let timestamp =
.resources c.resources.timestamper.latest_timestamp().unwrap_or(None); // Ignore data from timer capture overflows.
.timestamper
.latest_timestamp()
.unwrap_or(None) // Ignore data from timer capture overflows.
.map(|t| t as i32);
let (pll_phase, pll_frequency) = c.resources.pll.update( let (pll_phase, pll_frequency) = c.resources.pll.update(
timestamp, timestamp.map(|t| t as i32),
settings.pll_tc[0], settings.pll_tc[0],
settings.pll_tc[1], settings.pll_tc[1],
); );
@ -184,12 +180,18 @@ const APP: () = {
.unwrap() .unwrap()
* 2; // Full scale assuming the 2f component is gone. * 2; // Full scale assuming the 2f component is gone.
let output = match settings.output_conf { let output = [
// Convert from IQ to power and phase. match settings.output_conf[0] {
Conf::PowerPhase => [(output.log2() << 24) as _, output.arg()], Conf::PowerPhase => output.abs_sqr() as _,
Conf::FrequencyDiscriminator => [pll_frequency as _, output.arg()], Conf::FrequencyDiscriminator => (output.log2() << 24) as _,
Conf::Quadrature => [output.re, output.im], Conf::Quadrature => output.re,
}; },
match settings.output_conf[1] {
Conf::PowerPhase => output.arg(),
Conf::FrequencyDiscriminator => pll_frequency as _,
Conf::Quadrature => output.im,
},
];
// Convert to DAC data. // Convert to DAC data.
for i in 0..dac_samples[0].len() { for i in 0..dac_samples[0].len() {