lockin-external: expand output config
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6a96160cd0
commit
733d4243c3
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@ -34,13 +34,13 @@ pub struct Settings {
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lockin_harmonic: i32,
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lockin_harmonic: i32,
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lockin_phase: i32,
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lockin_phase: i32,
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output_conf: Conf,
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output_conf: [Conf; 2],
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}
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}
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impl Default for Settings {
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impl Default for Settings {
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fn default() -> Self {
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fn default() -> Self {
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Self {
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Self {
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afe: [AfeGain::G1, AfeGain::G1],
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afe: [AfeGain::G1; 2],
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pll_tc: [21, 21], // frequency and phase settling time (log2 counter cycles)
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pll_tc: [21, 21], // frequency and phase settling time (log2 counter cycles)
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@ -48,7 +48,7 @@ impl Default for Settings {
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lockin_harmonic: -1, // Harmonic index of the LO: -1 to _de_modulate the fundamental (complex conjugate)
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lockin_harmonic: -1, // Harmonic index of the LO: -1 to _de_modulate the fundamental (complex conjugate)
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lockin_phase: 0, // Demodulation LO phase offset
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lockin_phase: 0, // Demodulation LO phase offset
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output_conf: Conf::Quadrature,
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output_conf: [Conf::Quadrature; 2],
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}
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}
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}
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}
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}
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}
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@ -150,14 +150,10 @@ const APP: () = {
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let lockin = c.resources.lockin;
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let lockin = c.resources.lockin;
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let settings = c.resources.settings;
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let settings = c.resources.settings;
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let timestamp = c
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let timestamp =
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.resources
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c.resources.timestamper.latest_timestamp().unwrap_or(None); // Ignore data from timer capture overflows.
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.timestamper
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.latest_timestamp()
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.unwrap_or(None) // Ignore data from timer capture overflows.
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.map(|t| t as i32);
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let (pll_phase, pll_frequency) = c.resources.pll.update(
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let (pll_phase, pll_frequency) = c.resources.pll.update(
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timestamp,
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timestamp.map(|t| t as i32),
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settings.pll_tc[0],
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settings.pll_tc[0],
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settings.pll_tc[1],
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settings.pll_tc[1],
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);
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);
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@ -184,12 +180,18 @@ const APP: () = {
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.unwrap()
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.unwrap()
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* 2; // Full scale assuming the 2f component is gone.
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* 2; // Full scale assuming the 2f component is gone.
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let output = match settings.output_conf {
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let output = [
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// Convert from IQ to power and phase.
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match settings.output_conf[0] {
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Conf::PowerPhase => [(output.log2() << 24) as _, output.arg()],
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Conf::PowerPhase => output.abs_sqr() as _,
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Conf::FrequencyDiscriminator => [pll_frequency as _, output.arg()],
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Conf::FrequencyDiscriminator => (output.log2() << 24) as _,
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Conf::Quadrature => [output.re, output.im],
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Conf::Quadrature => output.re,
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};
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},
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match settings.output_conf[1] {
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Conf::PowerPhase => output.arg(),
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Conf::FrequencyDiscriminator => pll_frequency as _,
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Conf::Quadrature => output.im,
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},
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];
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// Convert to DAC data.
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// Convert to DAC data.
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for i in 0..dac_samples[0].len() {
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for i in 0..dac_samples[0].len() {
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