dma: don't swap buffers
* This uses a new closure-based method to the DMA HAL implementation which gives access to the inactive buffer directly. * It removes changing addresses, the third buffer for DBM, the inactive address poisoning, and allows the cancellation of the redundant repeat memory barriers and compiler fences. * This is now around 20 instructions per buffer down from about 100 cycles before. * Also introduces a new `SampleBuffer` type alias. * The required unpacking of the resources structure is a bit annoying but could probably abstraced away. TODO: * Test * Adapt `lockin`
This commit is contained in:
parent
d8cc3c74d9
commit
3165c680d6
3
Cargo.lock
generated
3
Cargo.lock
generated
@ -802,8 +802,7 @@ dependencies = [
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[[package]]
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name = "stm32h7xx-hal"
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version = "0.9.0"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "67034b80041bc33a48df1c1c435b6ae3bb18c35e42aa7e702ce8363b96793398"
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source = "git+https://github.com/quartiq/stm32h7xx-hal.git?rev=cca4ecc#cca4ecc3e0cc8cb2f7a9652c4099d50b44977493"
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dependencies = [
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"bare-metal 1.0.0",
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"cast",
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@ -56,7 +56,9 @@ rev = "523d71d"
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[dependencies.stm32h7xx-hal]
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features = ["stm32h743v", "rt", "unproven", "ethernet", "quadspi"]
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version = "0.9.0"
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# version = "0.9.0"
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git = "https://github.com/quartiq/stm32h7xx-hal.git"
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rev = "cca4ecc"
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[patch.crates-io.miniconf]
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git = "https://github.com/quartiq/miniconf.git"
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@ -2,6 +2,8 @@
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#![no_std]
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#![no_main]
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use core::sync::atomic::{fence, Ordering};
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use stabilizer::{hardware, net};
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use miniconf::Miniconf;
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@ -120,51 +122,73 @@ const APP: () = {
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/// Because the ADC and DAC operate at the same rate, these two constraints actually implement
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/// the same time bounds, meeting one also means the other is also met.
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#[task(binds=DMA1_STR4, resources=[adcs, digital_inputs, dacs, iir_state, settings, telemetry], priority=2)]
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fn process(c: process::Context) {
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let adc_samples = [
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c.resources.adcs.0.acquire_buffer(),
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c.resources.adcs.1.acquire_buffer(),
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];
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fn process(mut c: process::Context) {
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let adc0 = &mut c.resources.adcs.0;
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let adc1 = &mut c.resources.adcs.1;
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let dac0 = &mut c.resources.dacs.0;
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let dac1 = &mut c.resources.dacs.1;
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let di = &c.resources.digital_inputs;
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let settings = &c.resources.settings;
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let iir_state = &mut c.resources.iir_state;
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let telemetry = &mut c.resources.telemetry;
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adc0.with_buffer(|a0| {
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adc1.with_buffer(|a1| {
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dac0.with_buffer(|d0| {
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dac1.with_buffer(|d1| {
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let adc_samples = [a0, a1];
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let dac_samples = [d0, d1];
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let dac_samples = [
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c.resources.dacs.0.acquire_buffer(),
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c.resources.dacs.1.acquire_buffer(),
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];
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let digital_inputs =
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[di.0.is_high().unwrap(), di.1.is_high().unwrap()];
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let digital_inputs = [
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c.resources.digital_inputs.0.is_high().unwrap(),
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c.resources.digital_inputs.1.is_high().unwrap(),
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];
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let hold = settings.force_hold
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|| (digital_inputs[1] && settings.allow_hold);
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let hold = c.resources.settings.force_hold
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|| (digital_inputs[1] && c.resources.settings.allow_hold);
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// Preserve instruction and data ordering w.r.t. DMA flag access.
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fence(Ordering::SeqCst);
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for channel in 0..adc_samples.len() {
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for sample in 0..adc_samples[0].len() {
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let mut y = f32::from(adc_samples[channel][sample] as i16);
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for i in 0..c.resources.iir_state[channel].len() {
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y = c.resources.settings.iir_ch[channel][i].update(
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&mut c.resources.iir_state[channel][i],
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y,
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hold,
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);
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}
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// Note(unsafe): The filter limits ensure that the value is in range.
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adc_samples[channel]
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.iter()
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.zip(dac_samples[channel].iter_mut())
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.map(|(ai, di)| {
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let x = f32::from(*ai as i16);
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let y = settings.iir_ch[channel]
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.iter()
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.zip(iir_state[channel].iter_mut())
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.fold(x, |yi, (ch, state)| {
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ch.update(state, yi, hold)
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});
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// Note(unsafe): The filter limits must ensure that
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// the value is in range.
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// The truncation introduces 1/2 LSB distortion.
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let y = unsafe { y.to_int_unchecked::<i16>() };
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let y: i16 =
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unsafe { y.to_int_unchecked() };
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// Convert to DAC code
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dac_samples[channel][sample] = DacCode::from(y).0;
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}
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*di = DacCode::from(y).0;
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})
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.last();
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}
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// Update telemetry measurements.
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c.resources.telemetry.adcs =
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[AdcCode(adc_samples[0][0]), AdcCode(adc_samples[1][0])];
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telemetry.adcs = [
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AdcCode(adc_samples[0][0]),
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AdcCode(adc_samples[1][0]),
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];
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c.resources.telemetry.dacs =
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[DacCode(dac_samples[0][0]), DacCode(dac_samples[1][0])];
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telemetry.dacs = [
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DacCode(dac_samples[0][0]),
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DacCode(dac_samples[1][0]),
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];
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c.resources.telemetry.digital_inputs = digital_inputs;
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telemetry.digital_inputs = digital_inputs;
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// Preserve instruction and data ordering w.r.t. DMA flag access.
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fence(Ordering::SeqCst);
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})
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})
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})
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});
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}
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#[idle(resources=[network], spawn=[settings_update])]
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@ -29,15 +29,9 @@
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///! available. When enough samples have been collected, a transfer-complete interrupt is generated
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///! and the ADC samples are available for processing.
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///!
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///! The SPI peripheral internally has an 8- or 16-byte TX and RX FIFO, which corresponds to a 4- or
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///! 8-sample buffer for incoming ADC samples. During the handling of the DMA transfer completion,
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///! there is a small window where buffers are swapped over where it's possible that a sample could
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///! be lost. In order to avoid this, the SPI RX FIFO is effectively used as a "sample overflow"
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///! region and can buffer a number of samples until the next DMA transfer is configured. If a DMA
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///! transfer is still not set in time, the SPI peripheral will generate an input-overrun interrupt.
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///! This interrupt then serves as a means of detecting if samples have been lost, which will occur
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///! whenever data processing takes longer than the collection period.
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///!
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///! After a complete transfer of a batch of samples, the inactive buffer is available to the
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///! user for processing. The processing must complete before the DMA transfer of the next batch
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///! completes.
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///!
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///! ## Starting Data Collection
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///!
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@ -68,13 +62,12 @@
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///! sample DMA requests, which can be completed by setting e.g. ADC0's comparison to a counter
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///! value of 0 and ADC1's comparison to a counter value of 1.
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///!
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///! In this implementation, single buffer mode DMA transfers are used because the SPI RX FIFO can
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///! be used as a means to both detect and buffer ADC samples during the buffer swap-over. Because
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///! of this, double-buffered mode does not offer any advantages over single-buffered mode (unless
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///! double-buffered mode offers less overhead due to the DMA disable/enable procedure).
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///! In this implementation, double buffer mode DMA transfers are used because the SPI RX FIFOs
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///! have finite depth, FIFO access is slower than AXISRAM access, and because the single
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///! buffer mode DMA disable/enable and buffer update sequence is slow.
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use stm32h7xx_hal as hal;
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use super::design_parameters::SAMPLE_BUFFER_SIZE;
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use super::design_parameters::{SampleBuffer, SAMPLE_BUFFER_SIZE};
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use super::timers;
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use hal::dma::{
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@ -119,8 +112,7 @@ static mut SPI_EOT_CLEAR: [u32; 1] = [0x00];
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// processed). Note that the contents of AXI SRAM is uninitialized, so the buffer contents on
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// startup are undefined. The dimensions are `ADC_BUF[adc_index][ping_pong_index][sample_index]`.
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#[link_section = ".axisram.buffers"]
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static mut ADC_BUF: [[[u16; SAMPLE_BUFFER_SIZE]; 2]; 2] =
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[[[0; SAMPLE_BUFFER_SIZE]; 2]; 2];
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static mut ADC_BUF: [[SampleBuffer; 2]; 2] = [[[0; SAMPLE_BUFFER_SIZE]; 2]; 2];
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macro_rules! adc_input {
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($name:ident, $index:literal, $trigger_stream:ident, $data_stream:ident, $clear_stream:ident,
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@ -192,12 +184,11 @@ macro_rules! adc_input {
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/// Represents data associated with ADC.
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pub struct $name {
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next_buffer: Option<&'static mut [u16; SAMPLE_BUFFER_SIZE]>,
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transfer: Transfer<
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hal::dma::dma::$data_stream<hal::stm32::DMA1>,
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hal::spi::Spi<hal::stm32::$spi, hal::spi::Disabled, u16>,
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PeripheralToMemory,
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&'static mut [u16; SAMPLE_BUFFER_SIZE],
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&'static mut SampleBuffer,
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hal::dma::DBTransfer,
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>,
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trigger_transfer: Transfer<
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@ -316,6 +307,7 @@ macro_rules! adc_input {
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// data stream is used to trigger a transfer completion interrupt.
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let data_config = DmaConfig::default()
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.memory_increment(true)
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.double_buffer(true)
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.transfer_complete_interrupt($index == 1)
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.priority(Priority::VeryHigh);
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@ -333,17 +325,14 @@ macro_rules! adc_input {
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Transfer::init(
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data_stream,
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spi,
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// Note(unsafe): The ADC_BUF[$index][0] is "owned" by this peripheral.
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// Note(unsafe): The ADC_BUF[$index] is "owned" by this peripheral.
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// It shall not be used anywhere else in the module.
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unsafe { &mut ADC_BUF[$index][0] },
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None,
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unsafe { Some(&mut ADC_BUF[$index][1]) },
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data_config,
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);
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Self {
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// Note(unsafe): The ADC_BUF[$index][1] is "owned" by this peripheral. It
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// shall not be used anywhere else in the module.
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next_buffer: unsafe { Some(&mut ADC_BUF[$index][1]) },
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transfer: data_transfer,
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trigger_transfer,
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clear_transfer,
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@ -364,27 +353,17 @@ macro_rules! adc_input {
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}
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/// Obtain a buffer filled with ADC samples.
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/// Wait for the transfer of the currently active buffer to complete,
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/// then call a function on the now inactive buffer and acknowledge the
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/// transfer complete flag.
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///
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/// # Returns
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/// A reference to the underlying buffer that has been filled with ADC samples.
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pub fn acquire_buffer(&mut self) -> &[u16; SAMPLE_BUFFER_SIZE] {
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// Wait for the transfer to fully complete before continuing. Note: If a device
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// hangs up, check that this conditional is passing correctly, as there is no
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// time-out checks here in the interest of execution speed.
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while !self.transfer.get_transfer_complete_flag() {}
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let next_buffer = self.next_buffer.take().unwrap();
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// Start the next transfer.
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self.transfer.clear_interrupts();
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let (prev_buffer, _, _) =
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self.transfer.next_transfer(next_buffer).unwrap();
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// .unwrap_none() https://github.com/rust-lang/rust/issues/62633
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self.next_buffer.replace(prev_buffer);
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self.next_buffer.as_ref().unwrap()
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/// NOTE(unsafe): Memory safety and access ordering is not guaranteed
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/// (see the HAL DMA docs).
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pub fn with_buffer<F, R>(&mut self, f: F) -> R
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where
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F: FnOnce(&mut SampleBuffer) -> R,
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{
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unsafe { self.transfer.next_dbm_transfer_with(|buf, _current| f(buf)) }
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}
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}
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}
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///! served promptly after the transfer completes.
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use stm32h7xx_hal as hal;
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use super::design_parameters::SAMPLE_BUFFER_SIZE;
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use super::design_parameters::{SampleBuffer, SAMPLE_BUFFER_SIZE};
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use super::timers;
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use hal::dma::{
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@ -66,8 +66,7 @@ use hal::dma::{
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// processed). Note that the contents of AXI SRAM is uninitialized, so the buffer contents on
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// startup are undefined. The dimensions are `ADC_BUF[adc_index][ping_pong_index][sample_index]`.
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#[link_section = ".axisram.buffers"]
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static mut DAC_BUF: [[[u16; SAMPLE_BUFFER_SIZE]; 3]; 2] =
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[[[0; SAMPLE_BUFFER_SIZE]; 3]; 2];
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static mut DAC_BUF: [[SampleBuffer; 2]; 2] = [[[0; SAMPLE_BUFFER_SIZE]; 2]; 2];
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/// Custom type for referencing DAC output codes.
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/// The internal integer is the raw code written to the DAC output register.
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@ -137,13 +136,12 @@ macro_rules! dac_output {
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/// Represents data associated with DAC.
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pub struct $name {
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next_buffer: Option<&'static mut [u16; SAMPLE_BUFFER_SIZE]>,
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// Note: SPI TX functionality may not be used from this structure to ensure safety with DMA.
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transfer: Transfer<
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hal::dma::dma::$data_stream<hal::stm32::DMA1>,
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$spi,
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MemoryToPeripheral,
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&'static mut [u16; SAMPLE_BUFFER_SIZE],
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&'static mut SampleBuffer,
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hal::dma::DBTransfer,
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>,
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}
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@ -198,33 +196,26 @@ macro_rules! dac_output {
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trigger_config,
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);
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Self {
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transfer,
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// Note(unsafe): This buffer is only used once and provided for the next DMA transfer.
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next_buffer: unsafe { Some(&mut DAC_BUF[$index][2]) },
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}
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Self { transfer }
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}
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pub fn start(&mut self) {
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self.transfer.start(|spi| spi.start_dma());
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}
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/// Acquire the next output buffer to populate it with DAC codes.
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pub fn acquire_buffer(&mut self) -> &mut [u16; SAMPLE_BUFFER_SIZE] {
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// Note: If a device hangs up, check that this conditional is passing correctly, as
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// there is no time-out checks here in the interest of execution speed.
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while !self.transfer.get_transfer_complete_flag() {}
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let next_buffer = self.next_buffer.take().unwrap();
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// Start the next transfer.
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let (prev_buffer, _, _) =
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self.transfer.next_transfer(next_buffer).unwrap();
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// .unwrap_none() https://github.com/rust-lang/rust/issues/62633
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self.next_buffer.replace(prev_buffer);
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self.next_buffer.as_mut().unwrap()
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/// Wait for the transfer of the currently active buffer to complete,
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/// then call a function on the now inactive buffer and acknowledge the
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/// transfer complete flag.
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///
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/// NOTE(unsafe): Memory safety and access ordering is not guaranteed
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/// (see the HAL DMA docs).
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pub fn with_buffer<F, R>(&mut self, f: F) -> R
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where
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F: FnOnce(&mut SampleBuffer) -> R,
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{
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unsafe {
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self.transfer.next_dbm_transfer_with(|buf, _current| f(buf))
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}
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}
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}
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};
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@ -50,5 +50,7 @@ pub const ADC_SAMPLE_TICKS: u16 = 1 << ADC_SAMPLE_TICKS_LOG2;
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pub const SAMPLE_BUFFER_SIZE_LOG2: u8 = 3;
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pub const SAMPLE_BUFFER_SIZE: usize = 1 << SAMPLE_BUFFER_SIZE_LOG2;
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pub type SampleBuffer = [u16; SAMPLE_BUFFER_SIZE];
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// The MQTT broker IPv4 address
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pub const MQTT_BROKER: [u8; 4] = [10, 34, 16, 10];
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