dual-iir: destructure resources
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3165c680d6
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@ -123,14 +123,24 @@ const APP: () = {
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/// the same time bounds, meeting one also means the other is also met.
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/// the same time bounds, meeting one also means the other is also met.
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#[task(binds=DMA1_STR4, resources=[adcs, digital_inputs, dacs, iir_state, settings, telemetry], priority=2)]
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#[task(binds=DMA1_STR4, resources=[adcs, digital_inputs, dacs, iir_state, settings, telemetry], priority=2)]
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fn process(mut c: process::Context) {
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fn process(mut c: process::Context) {
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let adc0 = &mut c.resources.adcs.0;
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let process::Resources {
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let adc1 = &mut c.resources.adcs.1;
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adcs: (ref mut adc0, ref mut adc1),
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let dac0 = &mut c.resources.dacs.0;
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dacs: (ref mut dac0, ref mut dac1),
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let dac1 = &mut c.resources.dacs.1;
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ref digital_inputs,
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let di = &c.resources.digital_inputs;
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ref settings,
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let settings = &c.resources.settings;
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ref mut iir_state,
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let iir_state = &mut c.resources.iir_state;
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ref mut telemetry,
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let telemetry = &mut c.resources.telemetry;
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} = c.resources;
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let digital_inputs = [
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digital_inputs.0.is_high().unwrap(),
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digital_inputs.1.is_high().unwrap(),
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];
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telemetry.digital_inputs = digital_inputs;
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let hold =
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settings.force_hold || (digital_inputs[1] && settings.allow_hold);
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adc0.with_buffer(|a0| {
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adc0.with_buffer(|a0| {
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adc1.with_buffer(|a1| {
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adc1.with_buffer(|a1| {
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dac0.with_buffer(|d0| {
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dac0.with_buffer(|d0| {
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@ -138,12 +148,6 @@ const APP: () = {
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let adc_samples = [a0, a1];
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let adc_samples = [a0, a1];
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let dac_samples = [d0, d1];
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let dac_samples = [d0, d1];
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let digital_inputs =
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[di.0.is_high().unwrap(), di.1.is_high().unwrap()];
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let hold = settings.force_hold
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|| (digital_inputs[1] && settings.allow_hold);
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// Preserve instruction and data ordering w.r.t. DMA flag access.
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// Preserve instruction and data ordering w.r.t. DMA flag access.
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fence(Ordering::SeqCst);
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fence(Ordering::SeqCst);
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@ -181,8 +185,6 @@ const APP: () = {
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DacCode(dac_samples[1][0]),
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DacCode(dac_samples[1][0]),
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];
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];
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telemetry.digital_inputs = digital_inputs;
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// Preserve instruction and data ordering w.r.t. DMA flag access.
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// Preserve instruction and data ordering w.r.t. DMA flag access.
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fence(Ordering::SeqCst);
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fence(Ordering::SeqCst);
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})
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})
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