Adding WIP updates to using DMA
This commit is contained in:
parent
f56487401c
commit
20e9b6543c
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@ -185,6 +185,15 @@ dependencies = [
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"cortex-m",
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]
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[[package]]
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name = "embedded-dma"
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version = "0.1.2"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "46c8c02e4347a0267ca60813c952017f4c5948c232474c6010a381a337f1bda4"
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dependencies = [
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"stable_deref_trait",
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]
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[[package]]
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name = "embedded-hal"
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version = "0.2.4"
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@ -558,12 +567,12 @@ dependencies = [
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[[package]]
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name = "stm32h7xx-hal"
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version = "0.8.0"
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source = "git+https://github.com/quartiq/stm32h7xx-hal?branch=rs/issue-158/managed-spi#cc36bbbaa1bf21e53732cfc0f3dd7175c3ed6d44"
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dependencies = [
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"bare-metal 1.0.0",
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"cast",
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"cortex-m",
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"cortex-m-rt",
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"embedded-dma",
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"embedded-hal",
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"nb 1.0.0",
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"paste 1.0.2",
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@ -60,7 +60,7 @@ features = ["stm32h743v"]
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[dependencies.stm32h7xx-hal]
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features = ["stm32h743v", "rt", "unproven", "ethernet", "quadspi"]
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git = "https://github.com/quartiq/stm32h7xx-hal"
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branch = "rs/issue-158/managed-spi"
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branch = "feature/stabilizer-dma"
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[features]
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semihosting = ["panic-semihosting", "cortex-m-log/semihosting"]
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@ -70,7 +70,7 @@ nightly = ["cortex-m/inline-asm"]
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[profile.dev]
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codegen-units = 1
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incremental = false
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opt-level = 3
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opt-level = 1
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[profile.release]
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opt-level = 3
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@ -26,3 +26,6 @@ set var $t0=*$cc
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continue
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end
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#set var $t0=*$cc
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source ../../PyCortexMDebug/cmdebug/svd_gdb.py
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svd_load ~/Downloads/STM32H743x.svd
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292
src/main.rs
292
src/main.rs
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@ -35,9 +35,16 @@ use stm32h7xx_hal::prelude::*;
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use embedded_hal::digital::v2::{InputPin, OutputPin};
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use hal::{
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dma::{DmaChannel, DmaExt, DmaInternal},
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dma::{
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Transfer,
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PeripheralToMemory, MemoryToPeripheral,
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traits::{Stream, TargetAddress},
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dma::{
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DmaConfig,
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DMAReq,
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},
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},
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ethernet::{self, PHY},
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rcc::rec::ResetEnable,
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};
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use smoltcp as net;
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@ -46,12 +53,17 @@ use heapless::{consts::*, String};
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#[link_section = ".sram3.eth"]
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static mut DES_RING: ethernet::DesRing = ethernet::DesRing::new();
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mod dac;
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mod adc;
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mod afe;
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mod eeprom;
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mod iir;
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mod pounder;
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mod server;
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use dac::{Dac0Output, Dac1Output};
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use adc::{Adc0Input, Adc1Input};
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#[cfg(not(feature = "semihosting"))]
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fn init_log() {}
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@ -92,8 +104,6 @@ static mut NET_STORE: NetStorage = NetStorage {
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const SCALE: f32 = ((1 << 15) - 1) as f32;
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const SPI_START: u32 = 0x00;
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// static ETHERNET_PENDING: AtomicBool = AtomicBool::new(true);
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const TCP_RX_BUFFER_SIZE: usize = 8192;
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@ -163,12 +173,12 @@ macro_rules! route_request {
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#[rtic::app(device = stm32h7xx_hal::stm32, peripherals = true, monotonic = rtic::cyccnt::CYCCNT)]
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const APP: () = {
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struct Resources {
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adc0: hal::spi::Spi<hal::stm32::SPI2, hal::spi::Enabled, u16>,
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dac0: hal::spi::Spi<hal::stm32::SPI4, hal::spi::Enabled, u16>,
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adc0: Adc0Input,
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dac0: Dac0Output,
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afe0: AFE0,
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adc1: hal::spi::Spi<hal::stm32::SPI3, hal::spi::Enabled, u16>,
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dac1: hal::spi::Spi<hal::stm32::SPI5, hal::spi::Enabled, u16>,
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adc1: Adc1Input,
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dac1: Dac1Output,
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afe1: AFE1,
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eeprom_i2c: hal::i2c::I2c<hal::stm32::I2C2>,
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@ -247,11 +257,10 @@ const APP: () = {
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afe::ProgrammableGainAmplifier::new(a0_pin, a1_pin)
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};
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ccdr.peripheral.DMA1.reset().enable();
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let mut dma_channels = dp.DMA1.split();
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let dma_streams = hal::dma::dma::StreamsTuple::new(dp.DMA1, ccdr.peripheral.DMA1);
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// Configure the SPI interfaces to the ADCs and DACs.
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let adc0_spi = {
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let adc0 = {
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let spi_miso = gpiob
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.pb14
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.into_alternate_af5()
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@ -273,33 +282,7 @@ const APP: () = {
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.suspend_when_inactive()
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.cs_delay(220e-9);
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dma_channels.0.set_peripheral_address(
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&dp.SPI2.txdr as *const _ as u32,
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false,
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);
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dma_channels
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.0
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.set_memory_address(&SPI_START as *const _ as u32, false);
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dma_channels
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.0
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.set_direction(hal::dma::Direction::MemoryToPeripherial);
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dma_channels.0.set_transfer_length(1);
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dma_channels.0.cr().modify(|_, w| {
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w.circ()
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.enabled()
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.psize()
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.bits16()
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.msize()
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.bits16()
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.pfctrl()
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.dma()
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});
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dma_channels.0.dmamux().modify(|_, w| {
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w.dmareq_id()
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.variant(hal::stm32::dmamux1::ccr::DMAREQ_ID_A::TIM2_UP)
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});
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let mut spi: hal::spi::Spi<_, _, u16> = dp.SPI2.spi(
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let spi: hal::spi::Spi<_, _, u16> = dp.SPI2.spi(
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(spi_sck, spi_miso, hal::spi::NoMosi),
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config,
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50.mhz(),
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@ -307,16 +290,10 @@ const APP: () = {
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&ccdr.clocks,
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);
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// Kick-start the SPI transaction - we will add data to the TXFIFO to read from the ADC.
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let spi_regs = unsafe { &*hal::stm32::SPI2::ptr() };
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spi_regs.cr1.modify(|_, w| w.cstart().started());
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spi.listen(hal::spi::Event::Rxp);
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spi
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Adc0Input::new(spi, dma_streams.0, dma_streams.1)
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};
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let adc1_spi = {
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let adc1 = {
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let spi_miso = gpiob
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.pb4
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.into_alternate_af6()
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@ -338,33 +315,7 @@ const APP: () = {
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.suspend_when_inactive()
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.cs_delay(220e-9);
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dma_channels.1.set_peripheral_address(
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&dp.SPI3.txdr as *const _ as u32,
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false,
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);
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dma_channels
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.1
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.set_memory_address(&SPI_START as *const _ as u32, false);
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dma_channels
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.1
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.set_direction(hal::dma::Direction::MemoryToPeripherial);
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dma_channels.1.dmamux().modify(|_, w| {
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w.dmareq_id()
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.variant(hal::stm32::dmamux1::ccr::DMAREQ_ID_A::TIM2_UP)
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});
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dma_channels.1.set_transfer_length(1);
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dma_channels.1.cr().modify(|_, w| {
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w.circ()
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.enabled()
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.psize()
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.bits16()
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.msize()
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.bits16()
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.pfctrl()
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.dma()
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});
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let mut spi: hal::spi::Spi<_, _, u16> = dp.SPI3.spi(
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let spi: hal::spi::Spi<_, _, u16> = dp.SPI3.spi(
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(spi_sck, spi_miso, hal::spi::NoMosi),
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config,
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50.mhz(),
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@ -372,12 +323,7 @@ const APP: () = {
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&ccdr.clocks,
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);
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let spi_regs = unsafe { &*hal::stm32::SPI3::ptr() };
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spi_regs.cr1.modify(|_, w| w.cstart().started());
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spi.listen(hal::spi::Event::Rxp);
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spi
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Adc1Input::new(spi, dma_streams.2, dma_streams.3)
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};
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let _dac_clr_n = gpioe.pe12.into_push_pull_output().set_high().unwrap();
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@ -386,68 +332,76 @@ const APP: () = {
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let _dac1_ldac_n =
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gpioe.pe15.into_push_pull_output().set_low().unwrap();
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let dac0_spi = {
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let spi_miso = gpioe
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.pe5
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.into_alternate_af5()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let spi_sck = gpioe
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.pe2
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.into_alternate_af5()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let _spi_nss = gpioe
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.pe4
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.into_alternate_af5()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let dac0 = {
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let dac0_spi = {
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let spi_miso = gpioe
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.pe5
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.into_alternate_af5()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let spi_sck = gpioe
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.pe2
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.into_alternate_af5()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let _spi_nss = gpioe
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.pe4
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.into_alternate_af5()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let config = hal::spi::Config::new(hal::spi::Mode {
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polarity: hal::spi::Polarity::IdleHigh,
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phase: hal::spi::Phase::CaptureOnSecondTransition,
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})
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.manage_cs()
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.suspend_when_inactive()
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.communication_mode(hal::spi::CommunicationMode::Transmitter)
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.swap_mosi_miso();
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let config = hal::spi::Config::new(hal::spi::Mode {
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polarity: hal::spi::Polarity::IdleHigh,
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phase: hal::spi::Phase::CaptureOnSecondTransition,
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})
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.manage_cs()
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.suspend_when_inactive()
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.communication_mode(hal::spi::CommunicationMode::Transmitter)
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.swap_mosi_miso();
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dp.SPI4.spi(
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(spi_sck, spi_miso, hal::spi::NoMosi),
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config,
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50.mhz(),
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ccdr.peripheral.SPI4,
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&ccdr.clocks,
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)
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dp.SPI4.spi(
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(spi_sck, spi_miso, hal::spi::NoMosi),
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config,
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50.mhz(),
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ccdr.peripheral.SPI4,
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&ccdr.clocks,
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)
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};
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Dac0Output::new(dac0_spi)
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};
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let dac1_spi = {
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let spi_miso = gpiof
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.pf8
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.into_alternate_af5()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let spi_sck = gpiof
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.pf7
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.into_alternate_af5()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let _spi_nss = gpiof
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.pf6
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.into_alternate_af5()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let dac1 = {
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let dac1_spi = {
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let spi_miso = gpiof
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.pf8
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.into_alternate_af5()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let spi_sck = gpiof
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.pf7
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.into_alternate_af5()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let _spi_nss = gpiof
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.pf6
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.into_alternate_af5()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let config = hal::spi::Config::new(hal::spi::Mode {
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polarity: hal::spi::Polarity::IdleHigh,
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phase: hal::spi::Phase::CaptureOnSecondTransition,
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})
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.manage_cs()
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.suspend_when_inactive()
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.communication_mode(hal::spi::CommunicationMode::Transmitter)
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.swap_mosi_miso();
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let config = hal::spi::Config::new(hal::spi::Mode {
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polarity: hal::spi::Polarity::IdleHigh,
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phase: hal::spi::Phase::CaptureOnSecondTransition,
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})
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.manage_cs()
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.communication_mode(hal::spi::CommunicationMode::Transmitter)
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.suspend_when_inactive()
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.swap_mosi_miso();
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dp.SPI5.spi(
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(spi_sck, spi_miso, hal::spi::NoMosi),
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config,
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50.mhz(),
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ccdr.peripheral.SPI5,
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&ccdr.clocks,
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)
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dp.SPI5.spi(
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(spi_sck, spi_miso, hal::spi::NoMosi),
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config,
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50.mhz(),
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ccdr.peripheral.SPI5,
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&ccdr.clocks,
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)
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};
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Dac1Output::new(dac1_spi)
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};
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let mut fp_led_0 = gpiod.pd5.into_push_pull_output();
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@ -728,24 +682,20 @@ const APP: () = {
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// Configure timer 2 to trigger conversions for the ADC
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let timer2 =
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dp.TIM2.timer(500.khz(), ccdr.peripheral.TIM2, &ccdr.clocks);
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dp.TIM2.timer(50.khz(), ccdr.peripheral.TIM2, &ccdr.clocks);
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{
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let t2_regs = unsafe { &*hal::stm32::TIM2::ptr() };
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t2_regs.dier.modify(|_, w| w.ude().set_bit());
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}
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// Start the SPI transfers.
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dma_channels.0.start();
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dma_channels.1.start();
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init::LateResources {
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afe0: afe0,
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adc0: adc0_spi,
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dac0: dac0_spi,
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adc0: adc0,
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dac0: dac0,
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afe1: afe1,
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adc1: adc1_spi,
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dac1: dac1_spi,
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adc1: adc1,
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dac1: dac1,
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timer: timer2,
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pounder: pounder_devices,
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@ -757,30 +707,34 @@ const APP: () = {
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}
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}
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#[task(binds = SPI3, resources = [adc1, dac1, iir_state, iir_ch], priority = 2)]
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fn spi3(c: spi3::Context) {
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let output: u16 = {
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let a: u16 = c.resources.adc1.read().unwrap();
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let x0 = f32::from(a as i16);
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let y0 =
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c.resources.iir_ch[1].update(&mut c.resources.iir_state[1], x0);
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y0 as i16 as u16 ^ 0x8000
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};
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#[task(binds=DMA1_STR3, resources=[adc1, dac1, iir_state, iir_ch], priority=2)]
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fn adc1(c: adc1::Context) {
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let samples = c.resources.adc1.transfer_complete_handler();
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c.resources.dac1.send(output).unwrap();
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let mut last_result: u16 = 0;
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for sample in samples {
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let x0 = f32::from(*sample as i16);
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let y0 = c.resources.iir_ch[1].update(&mut c.resources.iir_state[1], x0);
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last_result = y0 as i16 as u16 ^ 0x8000;
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//c.resources.dac0.push(last_result);
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}
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c.resources.dac1.write(last_result);
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}
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#[task(binds = SPI2, resources = [adc0, dac0, iir_state, iir_ch], priority = 2)]
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fn spi2(c: spi2::Context) {
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let output: u16 = {
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let a: u16 = c.resources.adc0.read().unwrap();
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let x0 = f32::from(a as i16);
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let y0 =
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c.resources.iir_ch[0].update(&mut c.resources.iir_state[0], x0);
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y0 as i16 as u16 ^ 0x8000
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};
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#[task(binds=DMA1_STR1, resources=[adc0, dac0, iir_state, iir_ch], priority=2)]
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fn adc0(c: adc0::Context) {
|
||||
let samples = c.resources.adc0.transfer_complete_handler();
|
||||
|
||||
c.resources.dac0.send(output).unwrap();
|
||||
let mut last_result: u16 = 0;
|
||||
for sample in samples {
|
||||
let x0 = f32::from(*sample as i16);
|
||||
let y0 = c.resources.iir_ch[0].update(&mut c.resources.iir_state[0], x0);
|
||||
last_result = y0 as i16 as u16 ^ 0x8000;
|
||||
//c.resources.dac0.push(last_result);
|
||||
}
|
||||
|
||||
c.resources.dac0.write(last_result);
|
||||
}
|
||||
|
||||
#[idle(resources=[net_interface, pounder, mac_addr, eth_mac, iir_state, iir_ch, afe0, afe1])]
|
||||
|
|
@ -973,6 +927,16 @@ const APP: () = {
|
|||
unsafe { ethernet::interrupt_handler() }
|
||||
}
|
||||
|
||||
#[task(binds = SPI2, priority = 1)]
|
||||
fn spi2(_: spi2::Context) {
|
||||
panic!("ADC0 input overrun");
|
||||
}
|
||||
|
||||
#[task(binds = SPI3, priority = 1)]
|
||||
fn spi3(_: spi3::Context) {
|
||||
panic!("ADC0 input overrun");
|
||||
}
|
||||
|
||||
extern "C" {
|
||||
// hw interrupt handlers for RTIC to use for scheduling tasks
|
||||
// one per priority
|
||||
|
|
|
|||
Loading…
Reference in New Issue