958 lines
34 KiB
Rust
958 lines
34 KiB
Rust
#![allow(clippy::missing_safety_doc)]
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#![no_std]
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#![no_main]
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#![cfg_attr(feature = "nightly", feature(asm))]
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// Enable returning `!`
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#![cfg_attr(feature = "nightly", feature(never_type))]
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#![cfg_attr(feature = "nightly", feature(core_intrinsics))]
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#[inline(never)]
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#[panic_handler]
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#[cfg(all(feature = "nightly", not(feature = "semihosting")))]
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fn panic(_info: &core::panic::PanicInfo) -> ! {
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let gpiod = unsafe { &*hal::stm32::GPIOD::ptr() };
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gpiod.odr.modify(|_, w| w.odr6().high().odr12().high()); // FP_LED_1, FP_LED_3
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unsafe {
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core::intrinsics::abort();
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}
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}
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#[cfg(feature = "semihosting")]
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extern crate panic_semihosting;
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#[cfg(not(any(feature = "nightly", feature = "semihosting")))]
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extern crate panic_halt;
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#[macro_use]
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extern crate log;
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// use core::sync::atomic::{AtomicU32, AtomicBool, Ordering};
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use cortex_m_rt::exception;
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use rtic::cyccnt::{Instant, U32Ext};
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use stm32h7xx_hal as hal;
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use stm32h7xx_hal::prelude::*;
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use embedded_hal::digital::v2::{InputPin, OutputPin};
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use hal::{
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dma::{
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Transfer,
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PeripheralToMemory, MemoryToPeripheral,
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traits::{Stream, TargetAddress},
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dma::{
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DmaConfig,
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DMAReq,
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},
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},
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ethernet::{self, PHY},
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};
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use smoltcp as net;
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use heapless::{consts::*, String};
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#[link_section = ".sram3.eth"]
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static mut DES_RING: ethernet::DesRing = ethernet::DesRing::new();
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mod dac;
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mod adc;
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mod afe;
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mod eeprom;
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mod iir;
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mod pounder;
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mod server;
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use dac::{Dac0Output, Dac1Output};
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use adc::{Adc0Input, Adc1Input};
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#[cfg(not(feature = "semihosting"))]
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fn init_log() {}
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#[cfg(feature = "semihosting")]
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fn init_log() {
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use cortex_m_log::log::{init as init_log, Logger};
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use cortex_m_log::printer::semihosting::{hio::HStdout, InterruptOk};
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use log::LevelFilter;
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static mut LOGGER: Option<Logger<InterruptOk<HStdout>>> = None;
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let logger = Logger {
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inner: InterruptOk::<_>::stdout().unwrap(),
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level: LevelFilter::Info,
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};
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let logger = unsafe { LOGGER.get_or_insert(logger) };
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init_log(logger).unwrap();
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}
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// Pull in build information (from `built` crate)
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mod build_info {
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#![allow(dead_code)]
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// include!(concat!(env!("OUT_DIR"), "/built.rs"));
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}
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pub struct NetStorage {
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ip_addrs: [net::wire::IpCidr; 1],
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neighbor_cache: [Option<(net::wire::IpAddress, net::iface::Neighbor)>; 8],
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}
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static mut NET_STORE: NetStorage = NetStorage {
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// Placeholder for the real IP address, which is initialized at runtime.
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ip_addrs: [net::wire::IpCidr::Ipv6(
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net::wire::Ipv6Cidr::SOLICITED_NODE_PREFIX,
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)],
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neighbor_cache: [None; 8],
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};
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const SCALE: f32 = ((1 << 15) - 1) as f32;
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// static ETHERNET_PENDING: AtomicBool = AtomicBool::new(true);
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const TCP_RX_BUFFER_SIZE: usize = 8192;
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const TCP_TX_BUFFER_SIZE: usize = 8192;
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type AFE0 = afe::ProgrammableGainAmplifier<
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hal::gpio::gpiof::PF2<hal::gpio::Output<hal::gpio::PushPull>>,
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hal::gpio::gpiof::PF5<hal::gpio::Output<hal::gpio::PushPull>>,
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>;
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type AFE1 = afe::ProgrammableGainAmplifier<
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hal::gpio::gpiod::PD14<hal::gpio::Output<hal::gpio::PushPull>>,
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hal::gpio::gpiod::PD15<hal::gpio::Output<hal::gpio::PushPull>>,
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>;
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macro_rules! route_request {
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($request:ident,
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readable_attributes: [$($read_attribute:tt: $getter:tt),*],
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modifiable_attributes: [$($write_attribute:tt: $TYPE:ty, $setter:tt),*]) => {
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match $request.req {
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server::AccessRequest::Read => {
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match $request.attribute {
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$(
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$read_attribute => {
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let value = match $getter() {
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Ok(data) => data,
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Err(_) => return server::Response::error($request.attribute,
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"Failed to read attribute"),
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};
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let encoded_data: String<U256> = match serde_json_core::to_string(&value) {
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Ok(data) => data,
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Err(_) => return server::Response::error($request.attribute,
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"Failed to encode attribute value"),
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};
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server::Response::success($request.attribute, &encoded_data)
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},
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)*
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_ => server::Response::error($request.attribute, "Unknown attribute")
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}
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},
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server::AccessRequest::Write => {
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match $request.attribute {
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$(
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$write_attribute => {
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let new_value = match serde_json_core::from_str::<$TYPE>(&$request.value) {
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Ok(data) => data,
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Err(_) => return server::Response::error($request.attribute,
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"Failed to decode value"),
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};
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match $setter(new_value) {
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Ok(_) => server::Response::success($request.attribute, &$request.value),
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Err(_) => server::Response::error($request.attribute,
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"Failed to set attribute"),
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}
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}
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)*
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_ => server::Response::error($request.attribute, "Unknown attribute")
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}
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}
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}
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}
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}
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#[rtic::app(device = stm32h7xx_hal::stm32, peripherals = true, monotonic = rtic::cyccnt::CYCCNT)]
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const APP: () = {
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struct Resources {
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adc0: Adc0Input,
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dac0: Dac0Output,
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afe0: AFE0,
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adc1: Adc1Input,
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dac1: Dac1Output,
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afe1: AFE1,
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eeprom_i2c: hal::i2c::I2c<hal::stm32::I2C2>,
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timer: hal::timer::Timer<hal::stm32::TIM2>,
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// Note: It appears that rustfmt generates a format that GDB cannot recognize, which
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// results in GDB breakpoints being set improperly.
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#[rustfmt::skip]
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net_interface: net::iface::EthernetInterface<
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'static,
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'static,
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'static,
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ethernet::EthernetDMA<'static>>,
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eth_mac: ethernet::phy::LAN8742A<ethernet::EthernetMAC>,
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mac_addr: net::wire::EthernetAddress,
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pounder: Option<pounder::PounderDevices<asm_delay::AsmDelay>>,
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#[init([[0.; 5]; 2])]
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iir_state: [iir::IIRState; 2],
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#[init([iir::IIR { ba: [1., 0., 0., 0., 0.], y_offset: 0., y_min: -SCALE - 1., y_max: SCALE }; 2])]
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iir_ch: [iir::IIR; 2],
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}
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#[init]
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fn init(c: init::Context) -> init::LateResources {
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let dp = c.device;
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let mut cp = c.core;
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let pwr = dp.PWR.constrain();
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let vos = pwr.freeze();
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// Enable SRAM3 for the ethernet descriptor ring.
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dp.RCC.ahb2enr.modify(|_, w| w.sram3en().set_bit());
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// Clear reset flags.
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dp.RCC.rsr.write(|w| w.rmvf().set_bit());
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// Select the PLLs for SPI.
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dp.RCC
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.d2ccip1r
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.modify(|_, w| w.spi123sel().pll2_p().spi45sel().pll2_q());
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let rcc = dp.RCC.constrain();
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let ccdr = rcc
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.use_hse(8.mhz())
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.sysclk(400.mhz())
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.hclk(200.mhz())
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.per_ck(100.mhz())
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.pll2_p_ck(100.mhz())
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.pll2_q_ck(100.mhz())
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.freeze(vos, &dp.SYSCFG);
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init_log();
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let mut delay = hal::delay::Delay::new(cp.SYST, ccdr.clocks);
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let gpioa = dp.GPIOA.split(ccdr.peripheral.GPIOA);
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let gpiob = dp.GPIOB.split(ccdr.peripheral.GPIOB);
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let gpioc = dp.GPIOC.split(ccdr.peripheral.GPIOC);
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let gpiod = dp.GPIOD.split(ccdr.peripheral.GPIOD);
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let gpioe = dp.GPIOE.split(ccdr.peripheral.GPIOE);
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let gpiof = dp.GPIOF.split(ccdr.peripheral.GPIOF);
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let gpiog = dp.GPIOG.split(ccdr.peripheral.GPIOG);
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let afe0 = {
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let a0_pin = gpiof.pf2.into_push_pull_output();
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let a1_pin = gpiof.pf5.into_push_pull_output();
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afe::ProgrammableGainAmplifier::new(a0_pin, a1_pin)
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};
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let afe1 = {
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let a0_pin = gpiod.pd14.into_push_pull_output();
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let a1_pin = gpiod.pd15.into_push_pull_output();
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afe::ProgrammableGainAmplifier::new(a0_pin, a1_pin)
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};
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let dma_streams = hal::dma::dma::StreamsTuple::new(dp.DMA1, ccdr.peripheral.DMA1);
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// Configure the SPI interfaces to the ADCs and DACs.
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let adc0 = {
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let spi_miso = gpiob
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.pb14
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.into_alternate_af5()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let spi_sck = gpiob
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.pb10
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.into_alternate_af5()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let _spi_nss = gpiob
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.pb9
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.into_alternate_af5()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let config = hal::spi::Config::new(hal::spi::Mode {
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polarity: hal::spi::Polarity::IdleHigh,
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phase: hal::spi::Phase::CaptureOnSecondTransition,
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})
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.manage_cs()
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.suspend_when_inactive()
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.cs_delay(220e-9);
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let spi: hal::spi::Spi<_, _, u16> = dp.SPI2.spi(
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(spi_sck, spi_miso, hal::spi::NoMosi),
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config,
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50.mhz(),
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ccdr.peripheral.SPI2,
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&ccdr.clocks,
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);
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Adc0Input::new(spi, dma_streams.0, dma_streams.1)
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};
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let adc1 = {
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let spi_miso = gpiob
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.pb4
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.into_alternate_af6()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let spi_sck = gpioc
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.pc10
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.into_alternate_af6()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let _spi_nss = gpioa
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.pa15
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.into_alternate_af6()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let config = hal::spi::Config::new(hal::spi::Mode {
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polarity: hal::spi::Polarity::IdleHigh,
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phase: hal::spi::Phase::CaptureOnSecondTransition,
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})
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.manage_cs()
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.suspend_when_inactive()
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.cs_delay(220e-9);
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let spi: hal::spi::Spi<_, _, u16> = dp.SPI3.spi(
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(spi_sck, spi_miso, hal::spi::NoMosi),
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config,
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50.mhz(),
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ccdr.peripheral.SPI3,
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&ccdr.clocks,
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);
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Adc1Input::new(spi, dma_streams.2, dma_streams.3)
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};
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let _dac_clr_n = gpioe.pe12.into_push_pull_output().set_high().unwrap();
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let _dac0_ldac_n =
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gpioe.pe11.into_push_pull_output().set_low().unwrap();
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let _dac1_ldac_n =
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gpioe.pe15.into_push_pull_output().set_low().unwrap();
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let dac0 = {
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let dac0_spi = {
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let spi_miso = gpioe
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.pe5
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.into_alternate_af5()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let spi_sck = gpioe
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.pe2
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.into_alternate_af5()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let _spi_nss = gpioe
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.pe4
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.into_alternate_af5()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let config = hal::spi::Config::new(hal::spi::Mode {
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polarity: hal::spi::Polarity::IdleHigh,
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phase: hal::spi::Phase::CaptureOnSecondTransition,
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})
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.manage_cs()
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.suspend_when_inactive()
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.communication_mode(hal::spi::CommunicationMode::Transmitter)
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.swap_mosi_miso();
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dp.SPI4.spi(
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(spi_sck, spi_miso, hal::spi::NoMosi),
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config,
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50.mhz(),
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ccdr.peripheral.SPI4,
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&ccdr.clocks,
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)
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};
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Dac0Output::new(dac0_spi)
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};
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let dac1 = {
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let dac1_spi = {
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let spi_miso = gpiof
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.pf8
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.into_alternate_af5()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let spi_sck = gpiof
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.pf7
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.into_alternate_af5()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let _spi_nss = gpiof
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.pf6
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.into_alternate_af5()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let config = hal::spi::Config::new(hal::spi::Mode {
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polarity: hal::spi::Polarity::IdleHigh,
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phase: hal::spi::Phase::CaptureOnSecondTransition,
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})
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.manage_cs()
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.communication_mode(hal::spi::CommunicationMode::Transmitter)
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.suspend_when_inactive()
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.swap_mosi_miso();
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dp.SPI5.spi(
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(spi_sck, spi_miso, hal::spi::NoMosi),
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config,
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50.mhz(),
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ccdr.peripheral.SPI5,
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&ccdr.clocks,
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)
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};
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Dac1Output::new(dac1_spi)
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};
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let mut fp_led_0 = gpiod.pd5.into_push_pull_output();
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let mut fp_led_1 = gpiod.pd6.into_push_pull_output();
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let mut fp_led_2 = gpiog.pg4.into_push_pull_output();
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let mut fp_led_3 = gpiod.pd12.into_push_pull_output();
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fp_led_0.set_low().unwrap();
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fp_led_1.set_low().unwrap();
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fp_led_2.set_low().unwrap();
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fp_led_3.set_low().unwrap();
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// Measure the Pounder PGOOD output to detect if pounder is present on Stabilizer.
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let pounder_pgood = gpiob.pb13.into_pull_down_input();
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delay.delay_ms(2u8);
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let pounder_devices = if pounder_pgood.is_high().unwrap() {
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let ad9959 = {
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let qspi_interface = {
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// Instantiate the QUADSPI pins and peripheral interface.
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let qspi_pins = {
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let _qspi_ncs = gpioc
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.pc11
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.into_alternate_af9()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let clk = gpiob
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.pb2
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.into_alternate_af9()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let io0 = gpioe
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.pe7
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.into_alternate_af10()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let io1 = gpioe
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.pe8
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.into_alternate_af10()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let io2 = gpioe
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.pe9
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.into_alternate_af10()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let io3 = gpioe
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.pe10
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.into_alternate_af10()
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.set_speed(hal::gpio::Speed::VeryHigh);
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(clk, io0, io1, io2, io3)
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};
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let qspi = hal::qspi::Qspi::bank2(
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dp.QUADSPI,
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qspi_pins,
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10.mhz(),
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&ccdr.clocks,
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ccdr.peripheral.QSPI,
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);
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pounder::QspiInterface::new(qspi).unwrap()
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};
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let mut reset_pin = gpioa.pa0.into_push_pull_output();
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let io_update = gpiog.pg7.into_push_pull_output();
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let asm_delay = {
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let frequency_hz = ccdr.clocks.c_ck().0;
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asm_delay::AsmDelay::new(asm_delay::bitrate::Hertz(
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frequency_hz,
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))
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};
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ad9959::Ad9959::new(
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qspi_interface,
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&mut reset_pin,
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io_update,
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asm_delay,
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ad9959::Mode::FourBitSerial,
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100_000_000f32,
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5,
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)
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.unwrap()
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};
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let io_expander = {
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let sda = gpiob.pb7.into_alternate_af4().set_open_drain();
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let scl = gpiob.pb8.into_alternate_af4().set_open_drain();
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let i2c1 = dp.I2C1.i2c(
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(scl, sda),
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|
100.khz(),
|
|
ccdr.peripheral.I2C1,
|
|
&ccdr.clocks,
|
|
);
|
|
mcp23017::MCP23017::default(i2c1).unwrap()
|
|
};
|
|
|
|
let spi = {
|
|
let spi_mosi = gpiod
|
|
.pd7
|
|
.into_alternate_af5()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let spi_miso = gpioa
|
|
.pa6
|
|
.into_alternate_af5()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let spi_sck = gpiog
|
|
.pg11
|
|
.into_alternate_af5()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
let config = hal::spi::Config::new(hal::spi::Mode {
|
|
polarity: hal::spi::Polarity::IdleHigh,
|
|
phase: hal::spi::Phase::CaptureOnSecondTransition,
|
|
});
|
|
|
|
// The maximum frequency of this SPI must be limited due to capacitance on the MISO
|
|
// line causing a long RC decay.
|
|
dp.SPI1.spi(
|
|
(spi_sck, spi_miso, spi_mosi),
|
|
config,
|
|
5.mhz(),
|
|
ccdr.peripheral.SPI1,
|
|
&ccdr.clocks,
|
|
)
|
|
};
|
|
|
|
let (adc1, adc2) = {
|
|
let (mut adc1, mut adc2) = hal::adc::adc12(
|
|
dp.ADC1,
|
|
dp.ADC2,
|
|
&mut delay,
|
|
ccdr.peripheral.ADC12,
|
|
&ccdr.clocks,
|
|
);
|
|
|
|
let adc1 = {
|
|
adc1.calibrate();
|
|
adc1.enable()
|
|
};
|
|
|
|
let adc2 = {
|
|
adc2.calibrate();
|
|
adc2.enable()
|
|
};
|
|
|
|
(adc1, adc2)
|
|
};
|
|
|
|
let adc1_in_p = gpiof.pf11.into_analog();
|
|
let adc2_in_p = gpiof.pf14.into_analog();
|
|
|
|
Some(
|
|
pounder::PounderDevices::new(
|
|
io_expander,
|
|
ad9959,
|
|
spi,
|
|
adc1,
|
|
adc2,
|
|
adc1_in_p,
|
|
adc2_in_p,
|
|
)
|
|
.unwrap(),
|
|
)
|
|
} else {
|
|
None
|
|
};
|
|
|
|
let mut eeprom_i2c = {
|
|
let sda = gpiof.pf0.into_alternate_af4().set_open_drain();
|
|
let scl = gpiof.pf1.into_alternate_af4().set_open_drain();
|
|
dp.I2C2.i2c(
|
|
(scl, sda),
|
|
100.khz(),
|
|
ccdr.peripheral.I2C2,
|
|
&ccdr.clocks,
|
|
)
|
|
};
|
|
|
|
// Configure ethernet pins.
|
|
{
|
|
// Reset the PHY before configuring pins.
|
|
let mut eth_phy_nrst = gpioe.pe3.into_push_pull_output();
|
|
eth_phy_nrst.set_low().unwrap();
|
|
delay.delay_us(200u8);
|
|
eth_phy_nrst.set_high().unwrap();
|
|
let _rmii_ref_clk = gpioa
|
|
.pa1
|
|
.into_alternate_af11()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let _rmii_mdio = gpioa
|
|
.pa2
|
|
.into_alternate_af11()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let _rmii_mdc = gpioc
|
|
.pc1
|
|
.into_alternate_af11()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let _rmii_crs_dv = gpioa
|
|
.pa7
|
|
.into_alternate_af11()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let _rmii_rxd0 = gpioc
|
|
.pc4
|
|
.into_alternate_af11()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let _rmii_rxd1 = gpioc
|
|
.pc5
|
|
.into_alternate_af11()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let _rmii_tx_en = gpiob
|
|
.pb11
|
|
.into_alternate_af11()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let _rmii_txd0 = gpiob
|
|
.pb12
|
|
.into_alternate_af11()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let _rmii_txd1 = gpiog
|
|
.pg14
|
|
.into_alternate_af11()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
}
|
|
|
|
let mac_addr = match eeprom::read_eui48(&mut eeprom_i2c) {
|
|
Err(_) => {
|
|
info!("Could not read EEPROM, using default MAC address");
|
|
net::wire::EthernetAddress([0x10, 0xE2, 0xD5, 0x00, 0x03, 0x00])
|
|
}
|
|
Ok(raw_mac) => net::wire::EthernetAddress(raw_mac),
|
|
};
|
|
|
|
let (network_interface, eth_mac) = {
|
|
// Configure the ethernet controller
|
|
let (eth_dma, eth_mac) = unsafe {
|
|
ethernet::new_unchecked(
|
|
dp.ETHERNET_MAC,
|
|
dp.ETHERNET_MTL,
|
|
dp.ETHERNET_DMA,
|
|
&mut DES_RING,
|
|
mac_addr.clone(),
|
|
ccdr.peripheral.ETH1MAC,
|
|
&ccdr.clocks,
|
|
)
|
|
};
|
|
|
|
// Reset and initialize the ethernet phy.
|
|
let mut lan8742a =
|
|
ethernet::phy::LAN8742A::new(eth_mac.set_phy_addr(0));
|
|
lan8742a.phy_reset();
|
|
lan8742a.phy_init();
|
|
|
|
unsafe { ethernet::enable_interrupt() };
|
|
|
|
let store = unsafe { &mut NET_STORE };
|
|
|
|
store.ip_addrs[0] = net::wire::IpCidr::new(
|
|
net::wire::IpAddress::v4(10, 0, 16, 99),
|
|
24,
|
|
);
|
|
|
|
let neighbor_cache =
|
|
net::iface::NeighborCache::new(&mut store.neighbor_cache[..]);
|
|
|
|
let interface = net::iface::EthernetInterfaceBuilder::new(eth_dma)
|
|
.ethernet_addr(mac_addr)
|
|
.neighbor_cache(neighbor_cache)
|
|
.ip_addrs(&mut store.ip_addrs[..])
|
|
.finalize();
|
|
|
|
(interface, lan8742a)
|
|
};
|
|
|
|
cp.SCB.enable_icache();
|
|
|
|
// info!("Version {} {}", build_info::PKG_VERSION, build_info::GIT_VERSION.unwrap());
|
|
// info!("Built on {}", build_info::BUILT_TIME_UTC);
|
|
// info!("{} {}", build_info::RUSTC_VERSION, build_info::TARGET);
|
|
|
|
// Utilize the cycle counter for RTIC scheduling.
|
|
cp.DWT.enable_cycle_counter();
|
|
|
|
// Configure timer 2 to trigger conversions for the ADC
|
|
let timer2 =
|
|
dp.TIM2.timer(50.khz(), ccdr.peripheral.TIM2, &ccdr.clocks);
|
|
{
|
|
let t2_regs = unsafe { &*hal::stm32::TIM2::ptr() };
|
|
t2_regs.dier.modify(|_, w| w.ude().set_bit());
|
|
}
|
|
|
|
init::LateResources {
|
|
afe0: afe0,
|
|
adc0: adc0,
|
|
dac0: dac0,
|
|
|
|
afe1: afe1,
|
|
adc1: adc1,
|
|
dac1: dac1,
|
|
|
|
timer: timer2,
|
|
pounder: pounder_devices,
|
|
|
|
eeprom_i2c,
|
|
net_interface: network_interface,
|
|
eth_mac,
|
|
mac_addr,
|
|
}
|
|
}
|
|
|
|
#[task(binds=DMA1_STR3, resources=[adc1, dac1, iir_state, iir_ch], priority=2)]
|
|
fn adc1(c: adc1::Context) {
|
|
let samples = c.resources.adc1.transfer_complete_handler();
|
|
|
|
let mut last_result: u16 = 0;
|
|
for sample in samples {
|
|
let x0 = f32::from(*sample as i16);
|
|
let y0 = c.resources.iir_ch[1].update(&mut c.resources.iir_state[1], x0);
|
|
last_result = y0 as i16 as u16 ^ 0x8000;
|
|
//c.resources.dac0.push(last_result);
|
|
}
|
|
|
|
c.resources.dac1.write(last_result);
|
|
}
|
|
|
|
#[task(binds=DMA1_STR1, resources=[adc0, dac0, iir_state, iir_ch], priority=2)]
|
|
fn adc0(c: adc0::Context) {
|
|
let samples = c.resources.adc0.transfer_complete_handler();
|
|
|
|
let mut last_result: u16 = 0;
|
|
for sample in samples {
|
|
let x0 = f32::from(*sample as i16);
|
|
let y0 = c.resources.iir_ch[0].update(&mut c.resources.iir_state[0], x0);
|
|
last_result = y0 as i16 as u16 ^ 0x8000;
|
|
//c.resources.dac0.push(last_result);
|
|
}
|
|
|
|
c.resources.dac0.write(last_result);
|
|
}
|
|
|
|
#[idle(resources=[net_interface, pounder, mac_addr, eth_mac, iir_state, iir_ch, afe0, afe1])]
|
|
fn idle(mut c: idle::Context) -> ! {
|
|
let mut socket_set_entries: [_; 8] = Default::default();
|
|
let mut sockets =
|
|
net::socket::SocketSet::new(&mut socket_set_entries[..]);
|
|
|
|
let mut rx_storage = [0; TCP_RX_BUFFER_SIZE];
|
|
let mut tx_storage = [0; TCP_TX_BUFFER_SIZE];
|
|
let tcp_handle = {
|
|
let tcp_rx_buffer =
|
|
net::socket::TcpSocketBuffer::new(&mut rx_storage[..]);
|
|
let tcp_tx_buffer =
|
|
net::socket::TcpSocketBuffer::new(&mut tx_storage[..]);
|
|
let tcp_socket =
|
|
net::socket::TcpSocket::new(tcp_rx_buffer, tcp_tx_buffer);
|
|
sockets.add(tcp_socket)
|
|
};
|
|
|
|
let mut server = server::Server::new();
|
|
|
|
let mut time = 0u32;
|
|
let mut next_ms = Instant::now();
|
|
|
|
// TODO: Replace with reference to CPU clock from CCDR.
|
|
next_ms += 400_000.cycles();
|
|
|
|
loop {
|
|
let tick = Instant::now() > next_ms;
|
|
|
|
if tick {
|
|
next_ms += 400_000.cycles();
|
|
time += 1;
|
|
}
|
|
|
|
{
|
|
let socket =
|
|
&mut *sockets.get::<net::socket::TcpSocket>(tcp_handle);
|
|
if socket.state() == net::socket::TcpState::CloseWait {
|
|
socket.close();
|
|
} else if !(socket.is_open() || socket.is_listening()) {
|
|
socket
|
|
.listen(1235)
|
|
.unwrap_or_else(|e| warn!("TCP listen error: {:?}", e));
|
|
} else {
|
|
server.poll(socket, |req| {
|
|
info!("Got request: {:?}", req);
|
|
route_request!(req,
|
|
readable_attributes: [
|
|
"stabilizer/iir/state": (|| {
|
|
let state = c.resources.iir_state.lock(|iir_state|
|
|
server::Status {
|
|
t: time,
|
|
x0: iir_state[0][0],
|
|
y0: iir_state[0][2],
|
|
x1: iir_state[1][0],
|
|
y1: iir_state[1][2],
|
|
});
|
|
|
|
Ok::<server::Status, ()>(state)
|
|
}),
|
|
"stabilizer/afe0/gain": (|| c.resources.afe0.get_gain()),
|
|
"stabilizer/afe1/gain": (|| c.resources.afe1.get_gain()),
|
|
"pounder/in0": (|| {
|
|
match c.resources.pounder {
|
|
Some(pounder) =>
|
|
pounder.get_input_channel_state(pounder::Channel::In0),
|
|
_ => Err(pounder::Error::Access),
|
|
}
|
|
}),
|
|
"pounder/in1": (|| {
|
|
match c.resources.pounder {
|
|
Some(pounder) =>
|
|
pounder.get_input_channel_state(pounder::Channel::In1),
|
|
_ => Err(pounder::Error::Access),
|
|
}
|
|
}),
|
|
"pounder/out0": (|| {
|
|
match c.resources.pounder {
|
|
Some(pounder) =>
|
|
pounder.get_output_channel_state(pounder::Channel::Out0),
|
|
_ => Err(pounder::Error::Access),
|
|
}
|
|
}),
|
|
"pounder/out1": (|| {
|
|
match c.resources.pounder {
|
|
Some(pounder) =>
|
|
pounder.get_output_channel_state(pounder::Channel::Out1),
|
|
_ => Err(pounder::Error::Access),
|
|
}
|
|
}),
|
|
"pounder/dds/clock": (|| {
|
|
match c.resources.pounder {
|
|
Some(pounder) => pounder.get_dds_clock_config(),
|
|
_ => Err(pounder::Error::Access),
|
|
}
|
|
})
|
|
],
|
|
|
|
modifiable_attributes: [
|
|
"stabilizer/iir0/state": server::IirRequest, (|req: server::IirRequest| {
|
|
c.resources.iir_ch.lock(|iir_ch| {
|
|
if req.channel > 1 {
|
|
return Err(());
|
|
}
|
|
|
|
iir_ch[req.channel as usize] = req.iir;
|
|
|
|
Ok::<server::IirRequest, ()>(req)
|
|
})
|
|
}),
|
|
"stabilizer/iir1/state": server::IirRequest, (|req: server::IirRequest| {
|
|
c.resources.iir_ch.lock(|iir_ch| {
|
|
if req.channel > 1 {
|
|
return Err(());
|
|
}
|
|
|
|
iir_ch[req.channel as usize] = req.iir;
|
|
|
|
Ok::<server::IirRequest, ()>(req)
|
|
})
|
|
}),
|
|
"pounder/in0": pounder::ChannelState, (|state| {
|
|
match c.resources.pounder {
|
|
Some(pounder) =>
|
|
pounder.set_channel_state(pounder::Channel::In0, state),
|
|
_ => Err(pounder::Error::Access),
|
|
}
|
|
}),
|
|
"pounder/in1": pounder::ChannelState, (|state| {
|
|
match c.resources.pounder {
|
|
Some(pounder) =>
|
|
pounder.set_channel_state(pounder::Channel::In1, state),
|
|
_ => Err(pounder::Error::Access),
|
|
}
|
|
}),
|
|
"pounder/out0": pounder::ChannelState, (|state| {
|
|
match c.resources.pounder {
|
|
Some(pounder) =>
|
|
pounder.set_channel_state(pounder::Channel::Out0, state),
|
|
_ => Err(pounder::Error::Access),
|
|
}
|
|
}),
|
|
"pounder/out1": pounder::ChannelState, (|state| {
|
|
match c.resources.pounder {
|
|
Some(pounder) =>
|
|
pounder.set_channel_state(pounder::Channel::Out1, state),
|
|
_ => Err(pounder::Error::Access),
|
|
}
|
|
}),
|
|
"pounder/dds/clock": pounder::DdsClockConfig, (|config| {
|
|
match c.resources.pounder {
|
|
Some(pounder) => pounder.configure_dds_clock(config),
|
|
_ => Err(pounder::Error::Access),
|
|
}
|
|
}),
|
|
"stabilizer/afe0/gain": afe::Gain, (|gain| {
|
|
Ok::<(), ()>(c.resources.afe0.set_gain(gain))
|
|
}),
|
|
"stabilizer/afe1/gain": afe::Gain, (|gain| {
|
|
Ok::<(), ()>(c.resources.afe1.set_gain(gain))
|
|
})
|
|
]
|
|
)
|
|
});
|
|
}
|
|
}
|
|
|
|
let sleep = match c.resources.net_interface.poll(
|
|
&mut sockets,
|
|
net::time::Instant::from_millis(time as i64),
|
|
) {
|
|
Ok(changed) => changed == false,
|
|
Err(net::Error::Unrecognized) => true,
|
|
Err(e) => {
|
|
info!("iface poll error: {:?}", e);
|
|
true
|
|
}
|
|
};
|
|
|
|
if sleep {
|
|
cortex_m::asm::wfi();
|
|
}
|
|
}
|
|
}
|
|
|
|
#[task(binds = ETH, priority = 1)]
|
|
fn eth(_: eth::Context) {
|
|
unsafe { ethernet::interrupt_handler() }
|
|
}
|
|
|
|
#[task(binds = SPI2, priority = 1)]
|
|
fn spi2(_: spi2::Context) {
|
|
panic!("ADC0 input overrun");
|
|
}
|
|
|
|
#[task(binds = SPI3, priority = 1)]
|
|
fn spi3(_: spi3::Context) {
|
|
panic!("ADC0 input overrun");
|
|
}
|
|
|
|
extern "C" {
|
|
// hw interrupt handlers for RTIC to use for scheduling tasks
|
|
// one per priority
|
|
fn DCMI();
|
|
fn JPEG();
|
|
fn SDMMC();
|
|
}
|
|
};
|
|
|
|
#[exception]
|
|
fn HardFault(ef: &cortex_m_rt::ExceptionFrame) -> ! {
|
|
panic!("HardFault at {:#?}", ef);
|
|
}
|
|
|
|
#[exception]
|
|
fn DefaultHandler(irqn: i16) {
|
|
panic!("Unhandled exception (IRQn = {})", irqn);
|
|
}
|