pounder_test/src/hardware/design_parameters.rs

47 lines
2.1 KiB
Rust
Raw Normal View History

2021-01-18 23:47:47 +08:00
use stm32h7xx_hal::time::MegaHertz;
2021-01-05 00:12:24 +08:00
2020-11-25 00:09:36 +08:00
/// The ADC setup time is the number of seconds after the CSn line goes low before the serial clock
/// may begin. This is used for performing the internal ADC conversion.
pub const ADC_SETUP_TIME: f32 = 220e-9;
/// The maximum DAC/ADC serial clock line frequency. This is a hardware limit.
2021-01-05 00:12:24 +08:00
pub const ADC_DAC_SCK_MAX: MegaHertz = MegaHertz(50);
/// The optimal counting frequency of the hardware timers used for timestamping and sampling.
2021-01-05 00:12:24 +08:00
pub const TIMER_FREQUENCY: MegaHertz = MegaHertz(100);
2021-01-05 01:04:01 +08:00
/// The QSPI frequency for communicating with the pounder DDS.
2021-07-28 19:50:28 +08:00
pub const POUNDER_QSPI_FREQUENCY: MegaHertz = MegaHertz(100);
2021-01-05 01:04:01 +08:00
/// The delay after initiating a QSPI transfer before asserting the IO_Update for the pounder DDS.
2021-07-28 19:50:28 +08:00
// Pounder Profile writes are up to 16 bytes, with 2 cycles required per byte, coming out to a
// total of 32 QSPI clock cycles. The QSPI is configured for 100MHz, so this comes out to an offset
// of 320 ns. We use 400 ns to be safe.
pub const POUNDER_IO_UPDATE_DELAY: f32 = 400e-9;
2021-01-05 01:04:01 +08:00
/// The duration to assert IO_Update for the pounder DDS.
// IO_Update should be latched for 4 SYNC_CLK cycles after the QSPI profile write. With pounder
2021-01-06 21:59:01 +08:00
// SYNC_CLK running at 100MHz (1/4 of the pounder reference clock of 500MHz), this corresponds to
// 32ns. To accomodate rounding errors, we use 50ns instead.
2021-01-18 23:47:47 +08:00
pub const POUNDER_IO_UPDATE_DURATION: f32 = 50e-9;
/// The DDS reference clock frequency in MHz.
2021-01-06 21:59:01 +08:00
pub const DDS_REF_CLK: MegaHertz = MegaHertz(100);
/// The multiplier used for the DDS reference clock PLL.
pub const DDS_MULTIPLIER: u8 = 5;
2021-01-06 20:29:19 +08:00
/// The DDS system clock frequency after the internal PLL multiplication.
2021-01-06 22:04:06 +08:00
#[allow(dead_code)]
2021-01-06 21:59:01 +08:00
pub const DDS_SYSTEM_CLK: MegaHertz =
MegaHertz(DDS_REF_CLK.0 * DDS_MULTIPLIER as u32);
2021-01-06 20:29:19 +08:00
2021-01-06 21:59:01 +08:00
/// The divider from the DDS system clock to the SYNC_CLK output (sync-clk is always 1/4 of sysclk).
2021-01-06 22:04:06 +08:00
#[allow(dead_code)]
2021-01-06 21:59:01 +08:00
pub const DDS_SYNC_CLK_DIV: u8 = 4;
/// The maximum ADC/DAC sample processing buffer size.
pub const MAX_SAMPLE_BUFFER_SIZE: usize = 32;
pub type SampleBuffer = [u16; MAX_SAMPLE_BUFFER_SIZE];