8cd29672b0
rp_get_sayma_data: Remove unused module
2021-10-06 14:50:11 +08:00
00d47de59a
Update README
2021-06-18 15:49:39 +08:00
0ef521c516
Add auto test scripts for M-Labs and Creotech setups
2021-06-18 15:49:21 +08:00
cb891b7719
Update README
2021-05-13 10:37:32 +08:00
cf8b40d629
Remove RP uhubctl power control scripts
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* RP power will be controlled externally by test protocol definitions.
2021-05-13 10:37:32 +08:00
ef463c32a5
Add script for OS shutdown on RP
2021-05-13 10:37:31 +08:00
e46781a776
Add script for testing RP network connectivity
2021-05-13 10:27:51 +08:00
a5ba828b47
Add mlabs 2nd RP
2021-05-13 10:27:16 +08:00
001e981a65
rp_stop_uhubctl: Switch to SSH key auth for RP shutdown
2021-05-07 17:31:25 +08:00
698e90df1c
Update README
2021-05-07 16:32:04 +08:00
0fc9309748
Add RP power control scripts
2021-05-07 16:32:04 +08:00
781cae28b4
Style
2021-05-05 11:47:46 +08:00
c7f387f8d8
Update README
2021-04-28 21:57:58 +08:00
2cbf1f67bf
Add auto script for getting and plotting data from local RPs
2021-04-12 16:15:04 +08:00
276320d4c8
plot_sayma_data: Normalize data for plotting
2021-04-12 16:15:04 +08:00
64e85fc143
[WIP] Simplify ARTIQ scripts for DAC & TTL sync tests
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* A single `SyncDDSTTL` experiment definition can be used to test DAC and TTL outputs.
* For ST1/ST3, simply run this on Sayma gateware that produces hardcoded waves at SAWGs.
* For ST2/ST4, either:
* simply run this on Sayma gateware that produces hardcoded waves at both SAWGs and TTLs; or
* set `gen_ttl_wave=true` and run this on Sayma gateware that produces hardcoded waves at SAWGs only, while both MCXs are used as TTLOuts.
2021-04-12 16:15:04 +08:00
db4ae51030
mch_start: Improve message
2021-04-12 15:03:01 +08:00
33d81cdbdc
Add gain control & options for data collection/plotting; fix doc
2021-04-12 15:03:01 +08:00
bd792739c3
Add auto script for getting data on remote and plotting data on local
2021-03-09 17:02:10 +08:00
45367ac52f
Update RP data collection/plotting scripts with argparse & asyncio
2021-03-09 17:02:10 +08:00
fa0b190234
[WIP] Add preliminary ARTIQ scripts for ST1, ST2
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* For ST2, add the argument `ttl_use_fpga=true` to disable generating 111ns pulses on the TTLs.
2021-03-09 17:02:10 +08:00
a0d92497a9
Add ARTIQ device DB
2021-03-09 09:54:33 +08:00
7909267b88
Add RP data collection/plotting scripts
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* rp_get_sayma_data.py: to be installed on Creotech remote.
* plot_sayma_data.py: to be installed on local.
2021-02-22 17:43:48 +08:00
bf492e2f50
Add MCH control/logging scripts
2021-02-22 17:41:48 +08:00
4655ffffb7
Add /etc/udev/rules.d rules
2021-02-22 17:41:40 +08:00
914625d0ae
Initial commit
2021-02-22 17:39:27 +08:00
