forked from harry/creotech-sayma-testsuite
[WIP] Simplify ARTIQ scripts for DAC & TTL sync tests
* A single `SyncDDSTTL` experiment definition can be used to test DAC and TTL outputs. * For ST1/ST3, simply run this on Sayma gateware that produces hardcoded waves at SAWGs. * For ST2/ST4, either: * simply run this on Sayma gateware that produces hardcoded waves at both SAWGs and TTLs; or * set `gen_ttl_wave=true` and run this on Sayma gateware that produces hardcoded waves at SAWGs only, while both MCXs are used as TTLOuts.
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64e85fc143
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@ -47,7 +47,7 @@ for sayma in range(2):
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device_db["ttl" + str(sayma*2+i)] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLInOut",
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"class": "TTLOut",
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"arguments": {"channel": amc_base + 4+i},
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}
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@ -1,127 +0,0 @@
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# NOTES:
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# * Check DRTIO channel list by inspecting Metlino's log.
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# * Prepare an artiq_route .CFG to route Sayma#1 and #2 as LINK#1,2 and #3,4.
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from artiq.experiment import *
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def build_st1st2(exp):
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assert isinstance(exp, EnvExperiment)
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exp.setattr_device("core")
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# Test with SyncDDS channels
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exp.basemods_1 = [exp.get_device("basemod_att"+str(i)) for i in range(2)]
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exp.rfsws_1 = [exp.get_device("sawg_sw"+str(i)) for i in range(8)]
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exp.basemods_2 = [exp.get_device("basemod_att"+str(i)) for i in range(2, 4)]
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exp.rfsws_2 = [exp.get_device("sawg_sw"+str(i)) for i in range(8, 16)]
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# Test with 2 TTL channels
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exp.ttl_1 = exp.get_device("ttl0")
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exp.ttl_2 = exp.get_device("ttl2")
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# Bundled DUTs
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exp.basemods = exp.basemods_1 + exp.basemods_2
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exp.rfsws = exp.rfsws_1 + exp.rfsws_2
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exp.ttls = [exp.ttl_1, exp.ttl_2]
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class ST1(EnvExperiment):
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def build(self):
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build_st1st2(self)
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@kernel
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def drtio_is_up(self, drtio_index):
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if not self.core.get_rtio_destination_status(drtio_index):
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return False
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print("DRTIO #", drtio_index, "is ready\n")
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return True
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@kernel
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def run(self):
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print("*** Waiting for DRTIO ready...")
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drtio_indices = [1, 2, 3, 4]
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for i in drtio_indices:
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while not self.drtio_is_up(i):
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pass
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print("*** All DRTIO ready !")
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self.core.reset()
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for basemod in self.basemods:
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basemod.reset()
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delay(10*ms)
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basemod.set(6.0, 6.0, 6.0, 6.0)
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delay(10*ms)
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# Printing shows that the BaseMod is being controlled properly.
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print(basemod.get_mu())
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delay(500*ms)
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self.core.break_realtime()
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for rfsw in self.rfsws:
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rfsw.on()
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delay(1*ms)
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print("All RF switches are on.")
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while True:
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pass
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class ST2(EnvExperiment):
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def build(self):
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build_st1st2(self)
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# Option to switch TTL output source from RTIO PHY to FPGA (bypassing RTIO)
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self.setattr_argument("ttl_use_fpga", BooleanValue(False))
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@kernel
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def drtio_is_up(self, drtio_index):
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if not self.core.get_rtio_destination_status(drtio_index):
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return False
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print("DRTIO #", drtio_index, "is ready\n")
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return True
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@kernel
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def run(self):
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print("*** Waiting for DRTIO ready...")
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drtio_indices = [1, 2, 3, 4]
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for i in drtio_indices:
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while not self.drtio_is_up(i):
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pass
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print("*** All DRTIO ready !")
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self.core.reset()
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for basemod in self.basemods:
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basemod.reset()
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delay(10*ms)
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basemod.set(6.0, 6.0, 6.0, 6.0)
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delay(10*ms)
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# Printing shows that the BaseMod is being controlled properly.
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print(basemod.get_mu())
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delay(500*ms)
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self.core.break_realtime()
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for rfsw in self.rfsws:
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rfsw.on()
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delay(1*ms)
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print("All RF switches are on.")
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if self.ttl_use_fpga:
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while True:
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pass
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else:
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# test pulse
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self.core.break_realtime()
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for ttl in self.ttls:
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ttl.output()
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delay(1*ms)
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print("TTLs are now outputting pulses.")
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self.core.break_realtime()
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while True:
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with parallel:
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for ttl in self.ttls:
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ttl.on()
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delay(111*ns)
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with parallel:
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for ttl in self.ttls:
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ttl.off()
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delay(4444*ns)
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@ -0,0 +1,77 @@
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# NOTES:
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# * Check DRTIO channel list by inspecting Metlino's log.
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# * Prepare an artiq_route .CFG to route Sayma#1 and #2 as LINK#1,2 and #3,4.
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from artiq.experiment import *
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def build_exp(exp):
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assert isinstance(exp, EnvExperiment)
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exp.setattr_device("core")
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# Test with SyncDDS channels
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exp.basemods_1 = [exp.get_device("basemod_att"+str(i)) for i in range(2)]
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exp.rfsws_1 = [exp.get_device("sawg_sw"+str(i)) for i in range(8)]
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exp.basemods_2 = [exp.get_device("basemod_att"+str(i)) for i in range(2, 4)]
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exp.rfsws_2 = [exp.get_device("sawg_sw"+str(i)) for i in range(8, 16)]
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# Test with 2 TTL channels
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exp.ttl_1 = exp.get_device("ttl0")
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exp.ttl_2 = exp.get_device("ttl2")
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# Bundled DUTs
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exp.basemods = exp.basemods_1 + exp.basemods_2
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exp.rfsws = exp.rfsws_1 + exp.rfsws_2
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exp.ttls = [exp.ttl_1, exp.ttl_2]
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class SyncDDSTTL(EnvExperiment):
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def build(self):
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build_exp(self)
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# Option to use RTIO to generate TTL output
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self.setattr_argument("gen_ttl_wave", BooleanValue(False))
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@kernel
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def drtio_is_up(self, drtio_index):
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if not self.core.get_rtio_destination_status(drtio_index):
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return False
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print("DRTIO #", drtio_index, "is ready\n")
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return True
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@kernel
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def run(self):
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print("*** Waiting for DRTIO ready...")
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drtio_indices = [1, 2, 3, 4]
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for i in drtio_indices:
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while not self.drtio_is_up(i):
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pass
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print("*** All DRTIO ready !")
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self.core.reset()
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with parallel:
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with sequential:
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for basemod in self.basemods:
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basemod.reset()
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delay(10*ms)
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basemod.set(6.0, 6.0, 6.0, 6.0)
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delay(10*ms)
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# Printing shows that the BaseMod is being controlled properly.
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print(basemod.get_mu())
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delay(500*ms)
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delay(1*s)
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for rfsw in self.rfsws:
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rfsw.on()
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delay(1*ms)
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print("All RF switches are on, att = 6.0dB for each channel.")
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if self.gen_ttl_wave:
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# All MCX TTLs must be TTLOuts, not TTLInOuts
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print("TTLs are now outputting pulses with RTIO.")
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while True:
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for ttl in self.ttls:
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ttl.on()
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delay(111*ns)
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for ttl in self.ttls:
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ttl.off()
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delay(4444*ns)
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while True:
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pass
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