90904634cd
DDR: fixed register write.
...
Previously it writes `0x20066`, while the ps7_init set it to be
`0x200066`, notice the 1 more 0.
This should perform the same writes to the registers, so we do not have
to apply the ps7_init in artiq_zynq.
2020-07-06 11:46:37 +08:00
ae4d3e2455
smoltcp: enable IPv6
2020-07-06 11:30:48 +08:00
9fcf9243f2
simplify ps7_init
2020-07-06 00:52:40 +08:00
90e33f688a
FPU: moved enable function to zc706
2020-07-03 16:02:34 +08:00
f0697c3ec3
ddr: implement additional configuration
2020-07-03 02:20:10 +02:00
b2c707d543
ddr: remove superfluous _reg from register names
2020-07-03 02:20:10 +02:00
6195ad40c3
libsupport_zynq: make panic handler an optional feature
2020-06-29 10:05:46 +08:00
dd288912af
fix experiments build for Cora
2020-06-28 17:47:33 +08:00
ec252b099c
experiments: don't write raw blocks to the sdcard by default
2020-06-26 23:27:28 +02:00
a16c639eaf
experiments: add bandwidth tester
2020-06-26 22:36:52 +02:00
c6fa18344e
uncached: disable cachable/bufferable
2020-06-26 22:32:49 +02:00
5c69bbdad6
mmu: fix L1Table.update() flush
2020-06-26 22:31:56 +02:00
c0e66a632c
ps7_init: move from experiments to libboard_zynq
2020-06-25 01:40:42 +02:00
b129d3e0df
panic: fix CORE_MASK
2020-06-25 01:27:23 +02:00
1e4be13869
experiments: implement ps7_init::apply()
2020-06-25 01:27:02 +02:00
eea042e2ee
experiments: update ps7_init for zc706
2020-06-24 22:23:05 +02:00
b33ccf83ba
eth: doc
2020-06-18 18:07:50 +02:00
b4bcc6cf5c
TcpStream: add send_slice()
2020-06-18 01:56:49 +02:00
a80a2c67ef
eth: put desc list behind UncachedSlice, invalidate buffers, add barriers
2020-06-18 01:28:29 +02:00
d96343c249
uncached: refactor into UncachedSlice
2020-06-18 01:28:25 +02:00
ae739146c5
cache: add the required barriers
2020-06-18 01:27:34 +02:00
f50018092c
mmu: add early memory barrier to L1Table.update()
2020-06-18 01:27:34 +02:00
7c4d390ce4
libcortex_a9: start Uncached
2020-06-18 01:27:34 +02:00
6761575b30
mmu: add L1Table.update()
2020-06-18 01:27:34 +02:00
aebce435e2
mmu: switch bufferable=1 (writeback) for DDR pages
2020-06-18 01:27:34 +02:00
98f5099684
removed newline character
2020-06-16 17:36:01 +08:00
2c3fa991ad
implemented display trait for errors
2020-06-16 17:36:01 +08:00
2c14a2a1a2
fixed global timer reset
2020-06-16 17:31:37 +08:00
191da7c959
Added Copy trait for Milliseconds struct.
2020-06-16 14:56:29 +08:00
d52466cacf
DevC driver refactored.
2020-06-16 14:55:53 +08:00
a17a5d2925
sdcard: Changed some debug to trace.
2020-06-15 16:54:30 +08:00
e0f26871db
devc working!
2020-06-15 16:07:31 +08:00
82ec1ba7a7
sdio: better logging
2020-06-13 16:31:25 +08:00
d3b488bfb3
standard capacity support
2020-06-11 10:21:01 +08:00
074b3547de
sdio: fix unsound MaybeUninit usage
2020-06-11 10:07:19 +08:00
316ea61702
sdio: move ADMA2_DESCR32_TABLE into SdCard
2020-06-11 10:07:19 +08:00
1586190712
sdio: turn Adma2Desc32.attribute into a register!
2020-06-11 10:07:19 +08:00
32349e9dec
sdio: convert Adma2Desc32 to VolatileCells, make ADMA2_DESCR32_TABLE: MaybeUninit
2020-06-11 10:07:19 +08:00
b942cdcbc8
sdio: change Adma2Desc32 alignment from 1 to 4
...
this should not break anything.
2020-06-11 10:07:19 +08:00
a1a211334f
eth: always just allocate desc list + buffers
...
buffers are allocated vec anyway. this removes the lifetime hack and
further prepares work on cache-line alignment to enable L1 writeback.
2020-06-11 00:21:18 +02:00
187ef703f2
experiments: use stream.close() instead of .flush()
2020-06-10 20:21:01 +02:00
cf17a1c60a
removed unneeded methods
2020-06-10 12:55:22 +08:00
5332587de6
Changed mutability
2020-06-10 12:54:50 +08:00
0ebc4a61c8
Modified SDIO to handle u8 buffer instead of u32.
2020-06-09 17:03:17 +08:00
40d5eb8232
fixed compilation error
2020-06-05 12:27:41 +08:00
d01d0f69a4
formatting commit
2020-06-05 12:27:19 +08:00
236592ae66
SDIO module completed
2020-06-05 12:27:12 +08:00
a53ed8acc8
add remote run script
2020-06-04 19:57:52 +08:00
7695d6d8df
openocd: fix cora z7-10 PL_TAPID
2020-05-16 01:34:09 +02:00
2c82fb793e
Merge pull request 'sdio-registers' ( #29 )
2020-05-15 06:44:32 +08:00
