forked from M-Labs/zynq-rs
mmu: fix L1Table.update() flush
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@ -44,6 +44,15 @@ pub fn dcisw(setway: u32) {
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}
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}
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/// Data cache clean by set/way
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#[inline(always)]
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pub fn dccisw(setway: u32) {
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unsafe {
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llvm_asm!("mcr p15, 0, $0, c7, c14, 2" :: "r" (setway) :: "volatile");
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}
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}
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/// A made-up "instruction": invalidate all of the L1 D-Cache
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#[inline(always)]
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pub fn dciall() {
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@ -71,6 +80,33 @@ pub fn dciall() {
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}
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}
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/// A made-up "instruction": flush and invalidate all of the L1 D-Cache
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#[inline(always)]
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pub fn dcciall() {
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// the cache associativity could be read from a register, but will
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// always be 4 in L1 data cache of a cortex a9
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let ways = 4;
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let bit_pos_of_way = 30; // 32 - log2(ways)
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// the cache sets could be read from a register, but are always
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// 256 for the cores in the zync-7000; in general, 128 or 512 are
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// also possible.
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let sets = 256;
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let bit_pos_of_set = 5; // for a line size of 8 words = 2^5 bytes
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// select L1 data cache
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unsafe {
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llvm_asm!("mcr p15, 2, $0, c0, c0, 0" :: "r" (0) :: "volatile");
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}
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// Invalidate entire D-Cache by iterating every set and every way
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for set in 0..sets {
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for way in 0..ways {
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dccisw((set << bit_pos_of_set) | (way << bit_pos_of_way));
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}
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}
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}
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const CACHE_LINE: usize = 0x20;
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const CACHE_LINE_MASK: usize = CACHE_LINE - 1;
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@ -1,5 +1,5 @@
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use bit_field::BitField;
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use super::{regs::*, asm, cache};
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use super::{regs::*, asm::*, cache::*};
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use libregister::RegisterW;
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#[derive(Copy, Clone)]
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@ -368,10 +368,19 @@ impl L1Table {
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let result = f(&mut section);
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entry.set_section(section);
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asm::dmb();
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cache::tlbiall();
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asm::dsb();
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asm::isb();
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// Flush L1Dcache
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dcciall();
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// // TODO: L2?
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// Invalidate TLB
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tlbiall();
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// Invalidate all branch predictors
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bpiall();
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// ensure completion of the BP and TLB invalidation
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dsb();
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// synchronize context on this processor
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isb();
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result
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}
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@ -406,9 +415,9 @@ pub fn with_mmu<F: FnMut() -> !>(l1table: &L1Table, mut f: F) -> ! {
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// Synchronization barriers
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// Allows MMU to start
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asm::dsb();
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dsb();
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// Flushes pre-fetch buffer
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asm::isb();
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isb();
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f();
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}
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