1
0
Fork 0
Commit Graph

10 Commits

Author SHA1 Message Date
Astro a8886de067 zynq::ddr: implement configure_iob() 2019-10-24 01:24:12 +02:00
Astro 6bf210366a regs: properly emit doc_comments 2019-05-24 23:49:49 +02:00
Astro 179c617904 add register_bits_typed! macro 2019-05-23 18:29:05 +02:00
Astro 785e726661 RegisterW/RegisterRW: required &mut self for safety 2019-05-23 18:01:18 +02:00
Astro 5d02fe5c95 slcr: with_slcr() for unlock/lock 2019-05-21 01:30:17 +02:00
Astro 351d18c10f add register_at! macro 2019-05-20 23:01:50 +02:00
Astro 7872e00182 uart: move logic outside regs 2019-05-07 17:46:37 +02:00
Astro ca9b10dce8 refactor regs macros for RO/WO/RW access 2019-05-07 00:32:45 +02:00
Astro 1e540a1175 replace #[repr(packed)] with #[repr(C)]
avoids warnings regarding unsafe behaviour
2019-05-07 00:05:38 +02:00
Astro 55957eea09 regs macros 2019-05-06 23:56:53 +02:00