forked from M-Labs/zynq-rs
zynq::slcr: implement Display for PllStatus
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838434cdec
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a4d3360a70
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@ -1,4 +1,4 @@
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use crate::regs::RegisterR;
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use crate::regs::{RegisterR, RegisterRW};
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use super::slcr;
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#[cfg(feature = "target_zc706")]
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@ -89,4 +89,24 @@ impl CpuClocks {
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};
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pll / u32::from(uart_clk_ctrl.divisor())
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}
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pub fn enable_ddr(target_clock: u32) {
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let regs = slcr::RegisterBlock::new();
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regs.ddr_pll_ctrl.modify(|_, w| w
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.pll_pwrdwn(false)
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.pll_reset(true)
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.pll_bypass_force(true)
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);
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let fdiv = (target_clock / PS_CLK).max(127) as u16;
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regs.ddr_pll_ctrl.modify(|_, w| w
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.pll_pwrdwn(false)
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.pll_reset(false)
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.pll_fdiv(fdiv)
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);
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while ! regs.pll_status.read().ddr_pll_lock() {}
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regs.ddr_pll_ctrl.modify(|_, w| w
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.pll_bypass_force(false)
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.pll_bypass_qual(false)
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);
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}
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}
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@ -28,6 +28,8 @@ impl DdrRam {
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/// Zynq-7000 AP SoC Technical Reference Manual:
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/// 10.6.1 DDR Clock Initialization
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fn clock_setup(clocks: &CpuClocks) {
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CpuClocks::enable_ddr(1_066_000_000);
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let ddr3x_clk_divisor = ((clocks.ddr - 1) / DDR_FREQ + 1).min(255) as u8;
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let ddr2x_clk_divisor = 3 * ddr3x_clk_divisor / 2;
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@ -99,6 +101,7 @@ impl DdrRam {
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.output_en(slcr::DdriobOutputEn::Obuf);
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slcr.ddriob_addr0.write(addr_config.clone());
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slcr.ddriob_addr1.write(addr_config);
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let data_config = slcr::DdriobConfig::zeroed()
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.inp_type(slcr::DdriobInputType::VrefDifferential)
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.term_en(true)
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@ -106,6 +109,7 @@ impl DdrRam {
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.output_en(slcr::DdriobOutputEn::Obuf);
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slcr.ddriob_data0.write(data_config.clone());
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slcr.ddriob_data1.write(data_config);
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let diff_config = slcr::DdriobConfig::zeroed()
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.inp_type(slcr::DdriobInputType::Differential)
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.term_en(true)
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@ -113,6 +117,7 @@ impl DdrRam {
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.output_en(slcr::DdriobOutputEn::Obuf);
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slcr.ddriob_diff0.write(diff_config.clone());
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slcr.ddriob_diff1.write(diff_config);
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slcr.ddriob_clock.write(
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slcr::DdriobConfig::zeroed()
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.output_en(slcr::DdriobOutputEn::Obuf)
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@ -68,7 +68,7 @@ pub struct RegisterBlock {
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pub arm_pll_ctrl: PllCtrl,
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pub ddr_pll_ctrl: PllCtrl,
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pub io_pll_ctrl: PllCtrl,
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pub pll_status: RO<u32>,
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pub pll_status: PllStatus,
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pub arm_pll_cfg: PllCfg,
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pub ddr_pll_cfg: PllCfg,
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pub io_pll_cfg: PllCfg,
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@ -293,6 +293,27 @@ register_bit!(pll_ctrl, pll_bypass_qual, 3);
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register_bit!(pll_ctrl, pll_pwrdwn, 1);
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register_bit!(pll_ctrl, pll_reset, 0);
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register!(pll_status, PllStatus, RO, u32);
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register_bit!(pll_status, arm_pll_lock, 0);
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register_bit!(pll_status, ddr_pll_lock, 1);
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register_bit!(pll_status, io_pll_lock, 2);
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register_bit!(pll_status, arm_pll_stable, 3);
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register_bit!(pll_status, ddr_pll_stable, 4);
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register_bit!(pll_status, io_pll_stable, 5);
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impl core::fmt::Display for pll_status::Read {
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fn fmt(&self, fmt: &mut core::fmt::Formatter) -> Result<(), core::fmt::Error> {
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write!(fmt, "ARM: {}/{} DDR: {}/{} IO: {}/{}",
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if self.arm_pll_lock() { "locked" } else { "NOT locked" },
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if self.arm_pll_stable() { "stable" } else { "UNSTABLE" },
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if self.ddr_pll_lock() { "locked" } else { "NOT locked" },
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if self.ddr_pll_stable() { "stable" } else { "UNSTABLE" },
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if self.io_pll_lock() { "locked" } else { "NOT locked" },
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if self.io_pll_stable() { "stable" } else { "UNSTABLE" },
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)
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}
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}
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register!(pll_cfg, PllCfg, RW, u32);
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register_bits!(pll_cfg, pll_res, u8, 4, 7);
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register_bits!(pll_cfg, pll_cp, u8, 8, 11);
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