forked from M-Labs/zynq-rs
zynq::ddr: wait for init
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4cf5283ba8
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838434cdec
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@ -8,7 +8,9 @@ mod regs;
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const DDR_FREQ: u32 = 666_666_666;
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const DCI_FREQ: u32 = 10_000_000;
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pub struct DdrRam;
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pub struct DdrRam {
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regs: &'static mut regs::RegisterBlock,
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}
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impl DdrRam {
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pub fn new() -> Self {
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@ -16,9 +18,11 @@ impl DdrRam {
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Self::clock_setup(&clocks);
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Self::calibrate_iob_impedance(&clocks);
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Self::configure_iob();
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Self::reset_ddrc();
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DdrRam
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let regs = unsafe { regs::RegisterBlock::new() };
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let mut ddr = DdrRam { regs };
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ddr.reset_ddrc();
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ddr
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}
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/// Zynq-7000 AP SoC Technical Reference Manual:
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@ -133,15 +137,20 @@ impl DdrRam {
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}
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/// Reset DDR controller
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fn reset_ddrc() {
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let regs = unsafe { regs::RegisterBlock::new() };
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regs.ddrc_ctrl.modify(|_, w| w
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fn reset_ddrc(&mut self) {
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self.regs.ddrc_ctrl.modify(|_, w| w
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.soft_rstb(false)
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);
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regs.ddrc_ctrl.modify(|_, w| w
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self.regs.ddrc_ctrl.modify(|_, w| w
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.soft_rstb(true)
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.powerdown_en(false)
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.data_bus_width(regs::DataBusWidth::Width32bit)
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);
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while self.status() == regs::ControllerStatus::Init {}
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}
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pub fn status(&self) -> regs::ControllerStatus {
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self.regs.mode_sts_reg.read().operating_mode()
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}
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}
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@ -8,6 +8,21 @@ pub enum DataBusWidth {
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Width16bit = 0b01,
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}
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#[derive(Debug, Clone, PartialEq)]
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#[repr(u8)]
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pub enum ControllerStatus {
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Init = 0,
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Normal = 1,
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Powerdown = 2,
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SelfRefresh = 3,
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Powerdown1 = 4,
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Powerdown2 = 5,
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Powerdown3 = 6,
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Powerdown4 = 7,
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}
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#[repr(C)]
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pub struct RegisterBlock {
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pub ddrc_ctrl: DdrcCtrl,
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@ -31,7 +46,7 @@ pub struct RegisterBlock {
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pub dram_odt_reg: RW<u32>,
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pub phy_dbg_reg: RW<u32>,
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pub phy_cmd_timeout_rddata_cpt: RW<u32>,
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pub mode_sts_reg: RW<u32>,
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pub mode_sts_reg: ModeStsReg,
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pub dll_calib: RW<u32>,
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pub odt_delay_hold: RW<u32>,
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pub ctrl_reg1: RW<u32>,
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@ -154,3 +169,8 @@ register_bit!(ddrc_ctrl,
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register_bit!(ddrc_ctrl, powerdown_en, 1);
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register_bits_typed!(ddrc_ctrl, data_bus_width, u8, DataBusWidth, 2, 3);
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// (ddrc_ctrl) ...
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/// Controller operation mode status
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register!(mode_sts_reg, ModeStsReg, RO, u32);
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register_bits_typed!(mode_sts_reg, operating_mode, u8, ControllerStatus, 0, 2);
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// (mode_sts_reg) ...
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