linuswck 6cef418756 gateware: Add CSR Ctrl to PL's MMCM ... - Generate 45 Degree Phase Shifted DDR Clock - PLLE2_Base -> MMCM_ADV for ddr clock dynamic phase shift - Add mmcm_rst, ddr_clk_ps, mmcm_locked status to CSR - Generate dco2d rst signal from mmcm and connect to the related logic		2024-11-08 16:33:17 +08:00
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__init__.py	add fast-servo gateware support files	2024-03-01 16:39:56 +08:00
adc.py	gateware: Add CSR Ctrl to PL's MMCM	2024-11-08 16:33:17 +08:00
dac.py	gateware: Add CSR Ctrl to PL's MMCM	2024-11-08 16:33:17 +08:00
pitaya_ps.py	add fast-servo gateware support files	2024-03-01 16:39:56 +08:00
ps7.py	add fast-servo gateware support files	2024-03-01 16:39:56 +08:00
spi_phy.py	add fast-servo gateware support files	2024-03-01 16:39:56 +08:00