forked from M-Labs/nix-servo
add fast-servo gateware support files
This commit is contained in:
parent
e4dcc0e84a
commit
cd9590503c
5
fast-servo/linien-gateware/README.md
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5
fast-servo/linien-gateware/README.md
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## Source Repository
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Files in this directory were copied from [elhep/Fast-Servo-Frimware](https://github.com/elhep/Fast-Servo-Firmware/tree/master/fast_servo/gateware).
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## Commit ID
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The files were copied from commit ID [7fae40c](https://github.com/elhep/Fast-Servo-Firmware/commit/7fae40c0f872a91218be378f8289b98b1e366729).
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3
fast-servo/linien-gateware/__init__.py
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3
fast-servo/linien-gateware/__init__.py
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import os
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verilog_dir = os.path.join(os.path.abspath(os.path.dirname(__file__)), "verilog")
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0
fast-servo/linien-gateware/cores/__init__.py
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0
fast-servo/linien-gateware/cores/__init__.py
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179
fast-servo/linien-gateware/cores/adc.py
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179
fast-servo/linien-gateware/cores/adc.py
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# This file is part of Fast Servo Software Package.
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#
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# Copyright (C) 2023 Jakub Matyas
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# Warsaw University of Technology <jakubk.m@gmail.com>
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# SPDX-License-Identifier: GPL-3.0-or-later
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#
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# This program is free software: you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation, either version 3 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see <https://www.gnu.org/licenses/>.
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from migen import *
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from migen.genlib.cdc import MultiReg
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from misoc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage
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class _CRG(Module):
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def __init__(self, platform, dco_clk, dco_freq=200e6):
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self.clock_domains.cd_dco = ClockDomain()
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self.clock_domains.cd_dco2x = ClockDomain()
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self.clock_domains.cd_dco2d = ClockDomain()
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dco_clk_p, dco_clk_n = dco_clk
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dco_clk_buf = Signal()
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self.specials += Instance(
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"IBUFGDS", i_I=dco_clk_p, i_IB=dco_clk_n, o_O=dco_clk_buf
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)
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# # #
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clk_feedback = Signal()
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clk_feedback_buf = Signal()
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clk_dco = Signal()
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clk_dco2x = Signal()
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clk_dco2d = Signal()
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self.locked = Signal()
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platform.add_period_constraint(dco_clk_p, 1e9 / dco_freq)
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self.specials += [
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Instance(
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"PLLE2_BASE",
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p_BANDWIDTH="OPTIMIZED",
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p_DIVCLK_DIVIDE=1,
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p_CLKFBOUT_PHASE=0.0,
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p_CLKFBOUT_MULT=4, # VCO @ 800 MHz
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p_CLKIN1_PERIOD=(1e9 / dco_freq),
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p_REF_JITTER1=0.01,
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p_STARTUP_WAIT="FALSE",
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i_CLKIN1=dco_clk_buf,
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i_PWRDWN=0,
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i_RST=ResetSignal("sys"),
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i_CLKFBIN=clk_feedback_buf,
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o_CLKFBOUT=clk_feedback,
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p_CLKOUT0_DIVIDE=4,
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p_CLKOUT0_PHASE=0.0,
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p_CLKOUT0_DUTY_CYCLE=0.5,
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o_CLKOUT0=clk_dco, # 200 MHz <- dco_clk
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p_CLKOUT1_DIVIDE=2,
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p_CLKOUT1_PHASE=0.0,
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p_CLKOUT1_DUTY_CYCLE=0.5,
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o_CLKOUT1=clk_dco2x, # 400 MHZ <- 2 * dco_clk = 2*200 MHz
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p_CLKOUT2_DIVIDE=8,
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p_CLKOUT2_PHASE=0.0,
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p_CLKOUT2_DUTY_CYCLE=0.5,
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o_CLKOUT2=clk_dco2d, # 100 MHz <- dco_clk / 2 = 200 MHz / 2
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o_LOCKED=self.locked,
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)
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]
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self.specials += Instance("BUFG", i_I=clk_feedback, o_O=clk_feedback_buf)
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self.specials += Instance("BUFG", i_I=clk_dco, o_O=self.cd_dco.clk)
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self.specials += Instance("BUFG", i_I=clk_dco2d, o_O=self.cd_dco2d.clk)
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self.specials += Instance("BUFG", i_I=clk_dco2x, o_O=self.cd_dco2x.clk)
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class ADC(Module, AutoCSR):
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def __init__(self, platform, dco_freq=200e6):
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adc_pads = platform.request("adc")
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afe_pads = platform.request("adc_afe")
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self.frame_csr = CSRStatus(4)
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self.data_ch0 = CSRStatus(16)
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self.data_ch1 = CSRStatus(16)
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self.tap_delay = CSRStorage(5)
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self.bitslip_csr = CSRStorage(1)
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self.afe_ctrl = CSRStorage(4)
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tap_delay_val = Signal(5)
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bitslip = Signal()
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bitslip_re_dco_2d = Signal()
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ch1_gain_x10 = Signal()
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ch2_gain_x10 = Signal()
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ch1_shdn = Signal()
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ch2_shdn = Signal()
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self.data_out = [Signal(16, reset_less=True), Signal(16, reset_less=True)]
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self.s_frame = Signal(4)
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###
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# DCO clock coming from LTC2195
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# dco_clk = Record([("p", 1), ("n", 1)])
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dco_clk =(adc_pads.dco_p, adc_pads.dco_n)
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self.comb += [
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# dco_clk.p.eq(adc_pads.dco_p),
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# dco_clk.n.eq(adc_pads.dco_n),
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tap_delay_val.eq(self.tap_delay.storage),
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Cat(ch1_gain_x10, ch2_gain_x10, ch1_shdn, ch2_shdn).eq(
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self.afe_ctrl.storage
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),
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]
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self.submodules._crg = _CRG(platform, dco_clk, dco_freq)
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self.specials += MultiReg(self.bitslip_csr.re, bitslip_re_dco_2d, "dco2d")
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self.sync.dco2d += [
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bitslip.eq(Mux(bitslip_re_dco_2d, self.bitslip_csr.storage, 0))
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]
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self.comb += [
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self.frame_csr.status.eq(self.s_frame),
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self.data_ch0.status.eq(self.data_out[0]),
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self.data_ch1.status.eq(self.data_out[1]),
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]
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self.comb += [
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afe_pads.ch1_gain.eq(ch1_gain_x10),
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afe_pads.ch2_gain.eq(ch2_gain_x10),
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afe_pads.nshdn_ch1.eq(~ch1_shdn),
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afe_pads.nshdn_ch2.eq(~ch2_shdn),
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]
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dummy = Signal(8)
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dummy_idelay_rdy = Signal()
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self.specials += Instance(
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"LTC2195",
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i_rst_in=ResetSignal("sys"),
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i_clk200=ClockSignal("idelay"),
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i_DCO=ClockSignal("dco"),
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i_DCO_2D=ClockSignal("dco2d"),
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i_FR_in_p=adc_pads.frame_p,
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i_FR_in_n=adc_pads.frame_n,
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i_D0_in_p=adc_pads.data0_p,
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i_D0_in_n=adc_pads.data0_n,
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i_D1_in_p=adc_pads.data1_p,
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i_D1_in_n=adc_pads.data1_n,
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i_bitslip=bitslip,
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i_delay_val=tap_delay_val,
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o_ADC0_out=self.data_out[1], # LANES swapped on hardware
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o_ADC1_out=self.data_out[0],
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o_FR_out=self.s_frame,
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o_o_data_from_pins=dummy,
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o_idelay_rdy=dummy_idelay_rdy,
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)
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class AUX_ADC_CTRL(Module, AutoCSR):
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def __init__(self, platform):
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adc_aux_pads = platform.request("aux_adc")
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self.adc_aux_ctrl = CSRStorage(5)
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self.comb += [
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adc_aux_pads.diff_n.eq(~self.adc_aux_ctrl.storage[0]),
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adc_aux_pads.a.eq(self.adc_aux_ctrl.storage[1:4]),
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adc_aux_pads.range.eq(self.adc_aux_ctrl.storage[4]),
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]
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84
fast-servo/linien-gateware/cores/dac.py
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84
fast-servo/linien-gateware/cores/dac.py
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# This file is part of Fast Servo Software Package.
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#
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# Copyright (C) 2023 Jakub Matyas
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# Warsaw University of Technology <jakubk.m@gmail.com>
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# SPDX-License-Identifier: GPL-3.0-or-later
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#
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# This program is free software: you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation, either version 3 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
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# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <https://www.gnu.org/licenses/>.
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from migen import *
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from misoc.interconnect.csr import AutoCSR, CSRStorage
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from migen.genlib.io import DDROutput
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class DAC(Module, AutoCSR):
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def __init__(self, platform):
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dac_pads = platform.request("dac")
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dac_afe_pads = platform.request("dac_afe")
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self.dac_ctrl = CSRStorage(3)
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self.output_value_ch0 = CSRStorage(14)
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self.output_value_ch1 = CSRStorage(14)
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manual_override = Signal()
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ch0_pd = Signal()
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ch1_pd = Signal()
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output_data_ch0 = Signal(14)
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output_data_ch1 = Signal(14)
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self.data_in = [Signal(14, reset_less=True), Signal(14, reset_less=True)]
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platform.add_period_constraint(dac_pads.dclkio, 10.0)
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self.comb += [
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Cat(manual_override, ch0_pd, ch1_pd).eq(self.dac_ctrl.storage),
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dac_pads.rst.eq(ResetSignal("sys")),
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dac_afe_pads.ch1_pd_n.eq(~ch0_pd),
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dac_afe_pads.ch2_pd_n.eq(~ch1_pd),
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output_data_ch0.eq(
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Mux(manual_override, self.output_value_ch0.storage, self.data_in[0])
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),
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output_data_ch1.eq(
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Mux(manual_override, self.output_value_ch1.storage, self.data_in[1])
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),
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]
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# data
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for lane in range(14):
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self.specials += DDROutput(
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i1 = output_data_ch0[lane],
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i2 = output_data_ch1[lane],
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o = dac_pads.data[lane],
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clk = ClockSignal("dco2d")
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)
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# clock forwarding
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self.specials += DDROutput(
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i1 = 0b0,
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i2 = 0b1,
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o = dac_pads.dclkio,
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clk = ClockSignal("dco2d"),
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)
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class AUX_DAC_CTRL(Module, AutoCSR):
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def __init__(self, platform):
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dac_aux_pads = platform.request("aux_dac")
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self.dac_aux_ctrl = CSRStorage(3)
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self.comb += [
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dac_aux_pads.nclr.eq(~self.dac_aux_ctrl.storage[0]),
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dac_aux_pads.bin.eq(self.dac_aux_ctrl.storage[1]),
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dac_aux_pads.nldac.eq(~self.dac_aux_ctrl.storage[2]),
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]
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385
fast-servo/linien-gateware/cores/pitaya_ps.py
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385
fast-servo/linien-gateware/cores/pitaya_ps.py
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@ -0,0 +1,385 @@
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# Copyright 2014-2015 Robert Jördens <jordens@gmail.com>
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# Copyright 2018-2022 Benjamin Wiegand <benjamin.wiegand@physik.hu-berlin.de>
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# Copyright 2021-2022 Bastian Leykauf <leykauf@physik.hu-berlin.de>
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# Copyright 2023 Jakub Matyas
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# Warsaw University of Technology <jakubk.m@gmail.com>
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#
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# This file is part of Fast Servo Software Package and is based on Linien.
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#
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# Linien is free software: you can redistribute it and/or modify
|
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# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation, either version 3 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
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# Linien is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with Linien. If not, see <http://www.gnu.org/licenses/>.
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from functools import reduce
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from operator import or_
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from migen import (
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DIR_M_TO_S,
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DIR_S_TO_M,
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Cat,
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ClockSignal,
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If,
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Instance,
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Module,
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Record,
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Replicate,
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ResetSignal,
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Signal,
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)
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from misoc.interconnect import csr_bus, wishbone
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sys_layout = [
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("rstn", 1, DIR_M_TO_S),
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("clk", 1, DIR_M_TO_S),
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("addr", 32, DIR_M_TO_S),
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("wdata", 32, DIR_M_TO_S),
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("sel", 4, DIR_M_TO_S),
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("wen", 1, DIR_M_TO_S),
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("ren", 1, DIR_M_TO_S),
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("rdata", 32, DIR_S_TO_M),
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("err", 1, DIR_S_TO_M),
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("ack", 1, DIR_S_TO_M),
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]
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axi_layout = [
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("arvalid", 1),
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("awvalid", 1),
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("bready", 1),
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("rready", 1),
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("wlast", 1),
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("wvalid", 1),
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("arid", 12),
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("awid", 12),
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("wid", 12),
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("arburst", 2),
|
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("arlock", 2),
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("arsize", 3),
|
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("awburst", 2),
|
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("awlock", 2),
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("awsize", 3),
|
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("arprot", 3),
|
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("awprot", 3),
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("araddr", 32),
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("awaddr", 32),
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("wdata", 32),
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("arcache", 4),
|
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("arlen", 4),
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("arqos", 4),
|
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("awcache", 4),
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("awlen", 4),
|
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("awqos", 4),
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("wstrb", 4),
|
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("aclk", 1),
|
||||
("arready", 1),
|
||||
("awready", 1),
|
||||
("bvalid", 1),
|
||||
("rlast", 1),
|
||||
("rvalid", 1),
|
||||
("wready", 1),
|
||||
("bid", 12),
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("rid", 12),
|
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("bresp", 2),
|
||||
("rresp", 2),
|
||||
("rdata", 32),
|
||||
("arstn", 1),
|
||||
]
|
||||
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||||
|
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class PitayaPS(Module):
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def __init__(self, cpu):
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self.fclk = Signal(4)
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self.frstn = Signal(4)
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###
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self.submodules.axi = Axi2Sys()
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axi = self.axi.axi
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self.comb += [
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axi.aclk.eq(self.fclk[0]),
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axi.arstn.eq(self.frstn[0]),
|
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]
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self.specials += Instance(
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"system_processing_system7_0_0",
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io_MIO=cpu.mio,
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io_PS_CLK=cpu.ps_clk,
|
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io_PS_PORB=cpu.ps_porb,
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io_PS_SRSTB=cpu.ps_srstb,
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io_DDR_Addr=cpu.DDR_addr,
|
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io_DDR_BankAddr=cpu.DDR_ba,
|
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io_DDR_CAS_n=cpu.DDR_cas_n,
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io_DDR_Clk_n=cpu.DDR_ck_n,
|
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io_DDR_Clk=cpu.DDR_ck_p,
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io_DDR_CKE=cpu.DDR_cke,
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io_DDR_CS_n=cpu.DDR_cs_n,
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io_DDR_DM=cpu.DDR_dm,
|
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io_DDR_DQ=cpu.DDR_dq,
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||||
io_DDR_DQS_n=cpu.DDR_dqs_n,
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io_DDR_DQS=cpu.DDR_dqs_p,
|
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io_DDR_ODT=cpu.DDR_odt,
|
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io_DDR_RAS_n=cpu.DDR_ras_n,
|
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io_DDR_DRSTB=cpu.DDR_reset_n,
|
||||
io_DDR_WEB=cpu.DDR_we_n,
|
||||
io_DDR_VRN=cpu.ddr_vrn,
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||||
io_DDR_VRP=cpu.ddr_vrp,
|
||||
o_FCLK_CLK0=self.fclk[0],
|
||||
o_FCLK_CLK1=self.fclk[1],
|
||||
o_FCLK_CLK2=self.fclk[2],
|
||||
o_FCLK_CLK3=self.fclk[3],
|
||||
o_FCLK_RESET0_N=self.frstn[0],
|
||||
o_FCLK_RESET1_N=self.frstn[1],
|
||||
o_FCLK_RESET2_N=self.frstn[2],
|
||||
o_FCLK_RESET3_N=self.frstn[3],
|
||||
i_M_AXI_GP0_ACLK=axi.aclk,
|
||||
o_M_AXI_GP0_ARVALID=axi.arvalid,
|
||||
o_M_AXI_GP0_AWVALID=axi.awvalid,
|
||||
o_M_AXI_GP0_BREADY=axi.bready,
|
||||
o_M_AXI_GP0_RREADY=axi.rready,
|
||||
o_M_AXI_GP0_WLAST=axi.wlast,
|
||||
o_M_AXI_GP0_WVALID=axi.wvalid,
|
||||
o_M_AXI_GP0_ARID=axi.arid,
|
||||
o_M_AXI_GP0_AWID=axi.awid,
|
||||
o_M_AXI_GP0_WID=axi.wid,
|
||||
o_M_AXI_GP0_ARBURST=axi.arburst,
|
||||
o_M_AXI_GP0_ARLOCK=axi.arlock,
|
||||
o_M_AXI_GP0_ARSIZE=axi.arsize,
|
||||
o_M_AXI_GP0_AWBURST=axi.awburst,
|
||||
o_M_AXI_GP0_AWLOCK=axi.awlock,
|
||||
o_M_AXI_GP0_AWSIZE=axi.awsize,
|
||||
o_M_AXI_GP0_ARPROT=axi.arprot,
|
||||
o_M_AXI_GP0_AWPROT=axi.awprot,
|
||||
o_M_AXI_GP0_ARADDR=axi.araddr,
|
||||
o_M_AXI_GP0_AWADDR=axi.awaddr,
|
||||
o_M_AXI_GP0_WDATA=axi.wdata,
|
||||
o_M_AXI_GP0_ARCACHE=axi.arcache,
|
||||
o_M_AXI_GP0_ARLEN=axi.arlen,
|
||||
o_M_AXI_GP0_ARQOS=axi.arqos,
|
||||
o_M_AXI_GP0_AWCACHE=axi.awcache,
|
||||
o_M_AXI_GP0_AWLEN=axi.awlen,
|
||||
o_M_AXI_GP0_AWQOS=axi.awqos,
|
||||
o_M_AXI_GP0_WSTRB=axi.wstrb,
|
||||
i_M_AXI_GP0_ARREADY=axi.arready,
|
||||
i_M_AXI_GP0_AWREADY=axi.awready,
|
||||
i_M_AXI_GP0_BVALID=axi.bvalid,
|
||||
i_M_AXI_GP0_RLAST=axi.rlast,
|
||||
i_M_AXI_GP0_RVALID=axi.rvalid,
|
||||
i_M_AXI_GP0_WREADY=axi.wready,
|
||||
i_M_AXI_GP0_BID=axi.bid,
|
||||
i_M_AXI_GP0_RID=axi.rid,
|
||||
i_M_AXI_GP0_BRESP=axi.bresp,
|
||||
i_M_AXI_GP0_RRESP=axi.rresp,
|
||||
i_M_AXI_GP0_RDATA=axi.rdata,
|
||||
i_SPI0_SS_I=0,
|
||||
# i_SPI0_SS_I=spi.ss_i,
|
||||
# o_SPI0_SS_O=spi.ss_o,
|
||||
# o_SPI0_SS_T=spi.ss_t,
|
||||
# o_SPI0_SS1_O=spi.ss1_o,
|
||||
# o_SPI0_SS2_O=spi.ss2_o,
|
||||
i_SPI0_SCLK_I=0,
|
||||
# i_SPI0_SCLK_I=spi.sclk_i,
|
||||
# o_SPI0_SCLK_O=spi.sclk_o,
|
||||
# o_SPI0_SCLK_T=spi.sclk_t,
|
||||
i_SPI0_MOSI_I=0,
|
||||
# i_SPI0_MOSI_I=spi.mosi_i,
|
||||
# o_SPI0_MOSI_O=spi.mosi_o,
|
||||
# o_SPI0_MOSI_T=spi.mosi_t,
|
||||
i_SPI0_MISO_I=0,
|
||||
# i_SPI0_MISO_I=spi.miso_i,
|
||||
# o_SPI0_MISO_O=spi.miso_o,
|
||||
# o_SPI0_MISO_T=spi.miso_t,
|
||||
i_USB0_VBUS_PWRFAULT=0,
|
||||
)
|
||||
|
||||
|
||||
class Axi2Sys(Module):
|
||||
def __init__(self):
|
||||
self.sys = Record(sys_layout)
|
||||
self.axi = Record(axi_layout)
|
||||
|
||||
###
|
||||
|
||||
self.comb += [self.sys.clk.eq(self.axi.aclk), self.sys.rstn.eq(self.axi.arstn)]
|
||||
|
||||
self.specials += Instance(
|
||||
"axi_slave",
|
||||
p_AXI_DW=32,
|
||||
p_AXI_AW=32,
|
||||
p_AXI_IW=12,
|
||||
i_axi_clk_i=self.axi.aclk,
|
||||
i_axi_rstn_i=self.axi.arstn,
|
||||
i_axi_awid_i=self.axi.awid,
|
||||
i_axi_awaddr_i=self.axi.awaddr,
|
||||
i_axi_awlen_i=self.axi.awlen,
|
||||
i_axi_awsize_i=self.axi.awsize,
|
||||
i_axi_awburst_i=self.axi.awburst,
|
||||
i_axi_awlock_i=self.axi.awlock,
|
||||
i_axi_awcache_i=self.axi.awcache,
|
||||
i_axi_awprot_i=self.axi.awprot,
|
||||
i_axi_awvalid_i=self.axi.awvalid,
|
||||
o_axi_awready_o=self.axi.awready,
|
||||
i_axi_wid_i=self.axi.wid,
|
||||
i_axi_wdata_i=self.axi.wdata,
|
||||
i_axi_wstrb_i=self.axi.wstrb,
|
||||
i_axi_wlast_i=self.axi.wlast,
|
||||
i_axi_wvalid_i=self.axi.wvalid,
|
||||
o_axi_wready_o=self.axi.wready,
|
||||
o_axi_bid_o=self.axi.bid,
|
||||
o_axi_bresp_o=self.axi.bresp,
|
||||
o_axi_bvalid_o=self.axi.bvalid,
|
||||
i_axi_bready_i=self.axi.bready,
|
||||
i_axi_arid_i=self.axi.arid,
|
||||
i_axi_araddr_i=self.axi.araddr,
|
||||
i_axi_arlen_i=self.axi.arlen,
|
||||
i_axi_arsize_i=self.axi.arsize,
|
||||
i_axi_arburst_i=self.axi.arburst,
|
||||
i_axi_arlock_i=self.axi.arlock,
|
||||
i_axi_arcache_i=self.axi.arcache,
|
||||
i_axi_arprot_i=self.axi.arprot,
|
||||
i_axi_arvalid_i=self.axi.arvalid,
|
||||
o_axi_arready_o=self.axi.arready,
|
||||
o_axi_rid_o=self.axi.rid,
|
||||
o_axi_rdata_o=self.axi.rdata,
|
||||
o_axi_rresp_o=self.axi.rresp,
|
||||
o_axi_rlast_o=self.axi.rlast,
|
||||
o_axi_rvalid_o=self.axi.rvalid,
|
||||
i_axi_rready_i=self.axi.rready,
|
||||
o_sys_addr_o=self.sys.addr,
|
||||
o_sys_wdata_o=self.sys.wdata,
|
||||
o_sys_sel_o=self.sys.sel,
|
||||
o_sys_wen_o=self.sys.wen,
|
||||
o_sys_ren_o=self.sys.ren,
|
||||
i_sys_rdata_i=self.sys.rdata,
|
||||
i_sys_err_i=self.sys.err,
|
||||
i_sys_ack_i=self.sys.ack,
|
||||
)
|
||||
|
||||
|
||||
class SysInterconnect(Module):
|
||||
def __init__(self, master, *slaves):
|
||||
cs = Signal(max=len(slaves)) if len(slaves) != 1 else Signal()
|
||||
self.comb += cs.eq(master.addr[20:23])
|
||||
rets = []
|
||||
for i, s in enumerate(slaves):
|
||||
sel = Signal()
|
||||
self.comb += [
|
||||
sel.eq(cs == i),
|
||||
s.clk.eq(master.clk),
|
||||
s.rstn.eq(master.rstn),
|
||||
s.addr.eq(master.addr),
|
||||
s.wdata.eq(master.wdata),
|
||||
s.sel.eq(master.sel),
|
||||
s.wen.eq(sel & master.wen),
|
||||
s.ren.eq(sel & master.ren),
|
||||
]
|
||||
ret = Cat(s.err, s.ack, s.rdata)
|
||||
rets.append(Replicate(sel, len(ret)) & ret)
|
||||
self.comb += Cat(master.err, master.ack, master.rdata).eq(reduce(or_, rets))
|
||||
|
||||
|
||||
class Sys2Wishbone(Module):
|
||||
def __init__(self):
|
||||
self.wishbone = wb = wishbone.Interface()
|
||||
self.sys = sys = Record(sys_layout)
|
||||
|
||||
###
|
||||
|
||||
sys2 = Record(sys_layout)
|
||||
|
||||
self.specials += Instance(
|
||||
"bus_clk_bridge",
|
||||
i_sys_clk_i=sys.clk,
|
||||
i_sys_rstn_i=sys.rstn,
|
||||
i_sys_addr_i=sys.addr,
|
||||
i_sys_wdata_i=sys.wdata,
|
||||
i_sys_sel_i=sys.sel,
|
||||
i_sys_wen_i=sys.wen,
|
||||
i_sys_ren_i=sys.ren,
|
||||
o_sys_rdata_o=sys.rdata,
|
||||
o_sys_err_o=sys.err,
|
||||
o_sys_ack_o=sys.ack,
|
||||
i_clk_i=ClockSignal(),
|
||||
i_rstn_i=~ResetSignal(),
|
||||
o_addr_o=sys2.addr,
|
||||
o_wen_o=sys2.wen,
|
||||
o_ren_o=sys2.ren,
|
||||
o_wdata_o=sys2.wdata,
|
||||
i_rdata_i=sys2.rdata,
|
||||
i_err_i=sys2.err,
|
||||
i_ack_i=sys2.ack,
|
||||
)
|
||||
self.sync += [
|
||||
If(
|
||||
sys2.ren | sys2.wen,
|
||||
wb.cyc.eq(1),
|
||||
wb.adr.eq(sys2.addr[2:]),
|
||||
wb.we.eq(sys2.wen),
|
||||
wb.dat_w.eq(sys2.wdata),
|
||||
).Elif(wb.ack, wb.cyc.eq(0))
|
||||
]
|
||||
self.comb += [
|
||||
wb.stb.eq(wb.cyc),
|
||||
sys2.rdata.eq(wb.dat_r),
|
||||
sys2.ack.eq(wb.ack),
|
||||
sys2.err.eq(wb.err),
|
||||
]
|
||||
|
||||
|
||||
class SysCDC(Module):
|
||||
def __init__(self, cd_target="sys"):
|
||||
self.source = Record(sys_layout)
|
||||
self.target = Record(sys_layout)
|
||||
|
||||
self.specials += Instance(
|
||||
"bus_clk_bridge",
|
||||
i_sys_clk_i=self.source.clk,
|
||||
i_sys_rstn_i=self.source.rstn,
|
||||
i_sys_addr_i=self.source.addr,
|
||||
i_sys_wdata_i=self.source.wdata,
|
||||
i_sys_sel_i=self.source.sel,
|
||||
i_sys_wen_i=self.source.wen,
|
||||
i_sys_ren_i=self.source.ren,
|
||||
o_sys_rdata_o=self.source.rdata,
|
||||
o_sys_err_o=self.source.err,
|
||||
o_sys_ack_o=self.source.ack,
|
||||
i_clk_i=self.target.clk,
|
||||
i_rstn_i=self.target.rstn,
|
||||
o_addr_o=self.target.addr,
|
||||
o_wdata_o=self.target.wdata,
|
||||
o_wen_o=self.target.wen,
|
||||
o_ren_o=self.target.ren,
|
||||
i_rdata_i=self.target.rdata,
|
||||
i_err_i=self.target.err,
|
||||
i_ack_i=self.target.ack,
|
||||
)
|
||||
self.comb += [
|
||||
self.target.clk.eq(ClockSignal(cd_target)),
|
||||
self.target.rstn.eq(~ResetSignal(cd_target)),
|
||||
]
|
||||
|
||||
|
||||
class Sys2CSR(Module):
|
||||
def __init__(self):
|
||||
self.csr = csr_bus.Interface()
|
||||
self.sys = Record(sys_layout)
|
||||
|
||||
###
|
||||
|
||||
stb = Signal()
|
||||
self.sync += [
|
||||
stb.eq(self.sys.wen | self.sys.ren),
|
||||
self.csr.adr.eq(self.sys.addr[2:]),
|
||||
self.csr.we.eq(self.sys.wen),
|
||||
self.csr.dat_w.eq(self.sys.wdata),
|
||||
self.sys.ack.eq(stb),
|
||||
self.sys.rdata.eq(self.csr.dat_r),
|
||||
]
|
193
fast-servo/linien-gateware/cores/ps7.py
Normal file
193
fast-servo/linien-gateware/cores/ps7.py
Normal file
@ -0,0 +1,193 @@
|
||||
# This file is part of Fast Servo Software Package.
|
||||
#
|
||||
# Copyright (C) 2023 Jakub Matyas
|
||||
# Warsaw University of Technology <jakubk.m@gmail.com>
|
||||
# SPDX-License-Identifier: GPL-3.0-or-later
|
||||
#
|
||||
# This program is free software: you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation, either version 3 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <https://www.gnu.org/licenses/>.
|
||||
|
||||
from migen import *
|
||||
|
||||
|
||||
class PS7(Module):
|
||||
def __init__(self, platform, ps7_name=None):
|
||||
self.frstn = Signal()
|
||||
self.ps7_tcl = []
|
||||
self.platform = platform
|
||||
|
||||
self.ps7_name = "Zynq" if ps7_name is None else ps7_name
|
||||
|
||||
ps7_clk = platform.request("ps7_clk")
|
||||
ps7_porb = platform.request("ps7_porb")
|
||||
ps7_srstb = platform.request("ps7_srstb")
|
||||
ps7_mio = platform.request("ps7_mio")
|
||||
ps7_ddram = platform.request("ps7_ddram")
|
||||
|
||||
self.cpu_params = dict(
|
||||
# Clk / Rst.
|
||||
io_PS_CLK = ps7_clk,
|
||||
io_PS_PORB = ps7_porb,
|
||||
io_PS_SRSTB = ps7_srstb,
|
||||
|
||||
# MIO.
|
||||
io_MIO = ps7_mio,
|
||||
|
||||
# DDRAM.
|
||||
io_DDR_Addr = ps7_ddram.addr,
|
||||
io_DDR_BankAddr = ps7_ddram.ba,
|
||||
io_DDR_CAS_n = ps7_ddram.cas_n,
|
||||
io_DDR_Clk_n = ps7_ddram.ck_n,
|
||||
io_DDR_Clk = ps7_ddram.ck_p,
|
||||
io_DDR_CKE = ps7_ddram.cke,
|
||||
io_DDR_CS_n = ps7_ddram.cs_n,
|
||||
io_DDR_DM = ps7_ddram.dm,
|
||||
io_DDR_DQ = ps7_ddram.dq,
|
||||
io_DDR_DQS_n = ps7_ddram.dqs_n,
|
||||
io_DDR_DQS = ps7_ddram.dqs_p,
|
||||
io_DDR_ODT = ps7_ddram.odt,
|
||||
io_DDR_RAS_n = ps7_ddram.ras_n,
|
||||
io_DDR_DRSTB = ps7_ddram.reset_n,
|
||||
io_DDR_WEB = ps7_ddram.we_n,
|
||||
io_DDR_VRN = ps7_ddram.vrn,
|
||||
io_DDR_VRP = ps7_ddram.vrp,
|
||||
|
||||
# USB0.
|
||||
# i_USB0_VBUS_PWRFAULT = 0,
|
||||
|
||||
# Fabric Clk / Rst.
|
||||
# o_FCLK_CLK0 = ClockSignal("ps7"),
|
||||
o_FCLK_RESET0_N = self.frstn
|
||||
)
|
||||
|
||||
self.set_ps7(name=self.ps7_name,
|
||||
config={
|
||||
**self.platform.ps7_config
|
||||
})
|
||||
|
||||
def add_ps7_config(self, config):
|
||||
# Config must be provided as a config, value dict.
|
||||
assert isinstance(config, dict)
|
||||
# Add configs to PS7.
|
||||
self.ps7_tcl.append("set_property -dict [list \\")
|
||||
for config, value in config.items():
|
||||
self.ps7_tcl.append("CONFIG.{} {} \\".format(config, '{{' + str(value) + '}}'))
|
||||
self.ps7_tcl.append(f"] [get_ips {self.ps7_name}]")
|
||||
|
||||
def set_ps7(self, name=None, config=None, preset=None):
|
||||
self.ps7_name = name
|
||||
self.ps7_tcl.append(f"set ps7 [create_ip -vendor xilinx.com -name processing_system7 -module_name {self.ps7_name}]")
|
||||
self.add_ps7_config(config)
|
||||
|
||||
def add_axi_gp_master(self, interface):
|
||||
# assert type(interface) is Axi2Sys
|
||||
|
||||
axi_interface = interface
|
||||
|
||||
self.cpu_params.update({
|
||||
# AXI GP clk.
|
||||
f"i_M_AXI_GP0_ACLK" : axi_interface.aclk,
|
||||
|
||||
# AXI GP aw.
|
||||
f"o_M_AXI_GP0_AWVALID" : axi_interface.awvalid,
|
||||
f"i_M_AXI_GP0_AWREADY" : axi_interface.awready,
|
||||
f"o_M_AXI_GP0_AWADDR" : axi_interface.awaddr,
|
||||
f"o_M_AXI_GP0_AWBURST" : axi_interface.awburst,
|
||||
f"o_M_AXI_GP0_AWLEN" : axi_interface.awlen,
|
||||
f"o_M_AXI_GP0_AWSIZE" : axi_interface.awsize,
|
||||
f"o_M_AXI_GP0_AWID" : axi_interface.awid,
|
||||
f"o_M_AXI_GP0_AWLOCK" : axi_interface.awlock,
|
||||
f"o_M_AXI_GP0_AWPROT" : axi_interface.awprot,
|
||||
f"o_M_AXI_GP0_AWCACHE" : axi_interface.awcache,
|
||||
f"o_M_AXI_GP0_AWQOS" : axi_interface.awqos,
|
||||
|
||||
# AXI GP w.
|
||||
f"o_M_AXI_GP0_WVALID" : axi_interface.wvalid,
|
||||
f"o_M_AXI_GP0_WLAST" : axi_interface.wlast,
|
||||
f"i_M_AXI_GP0_WREADY" : axi_interface.wready,
|
||||
f"o_M_AXI_GP0_WID" : axi_interface.wid,
|
||||
f"o_M_AXI_GP0_WDATA" : axi_interface.wdata,
|
||||
f"o_M_AXI_GP0_WSTRB" : axi_interface.wstrb,
|
||||
|
||||
# AXI GP b.
|
||||
f"i_M_AXI_GP0_BVALID" : axi_interface.bvalid,
|
||||
f"o_M_AXI_GP0_BREADY" : axi_interface.bready,
|
||||
f"i_M_AXI_GP0_BID" : axi_interface.bid,
|
||||
f"i_M_AXI_GP0_BRESP" : axi_interface.bresp,
|
||||
|
||||
# AXI GP ar.
|
||||
f"o_M_AXI_GP0_ARVALID" : axi_interface.arvalid,
|
||||
f"i_M_AXI_GP0_ARREADY" : axi_interface.arready,
|
||||
f"o_M_AXI_GP0_ARADDR" : axi_interface.araddr,
|
||||
f"o_M_AXI_GP0_ARBURST" : axi_interface.arburst,
|
||||
f"o_M_AXI_GP0_ARLEN" : axi_interface.arlen,
|
||||
f"o_M_AXI_GP0_ARID" : axi_interface.arid,
|
||||
f"o_M_AXI_GP0_ARLOCK" : axi_interface.arlock,
|
||||
f"o_M_AXI_GP0_ARSIZE" : axi_interface.arsize,
|
||||
f"o_M_AXI_GP0_ARPROT" : axi_interface.arprot,
|
||||
f"o_M_AXI_GP0_ARCACHE" : axi_interface.arcache,
|
||||
f"o_M_AXI_GP0_ARQOS" : axi_interface.arqos,
|
||||
|
||||
# AXI GP r.
|
||||
f"i_M_AXI_GP0_RVALID" : axi_interface.rvalid,
|
||||
f"o_M_AXI_GP0_RREADY" : axi_interface.rready,
|
||||
f"i_M_AXI_GP0_RLAST" : axi_interface.rlast,
|
||||
f"i_M_AXI_GP0_RID" : axi_interface.rid,
|
||||
f"i_M_AXI_GP0_RRESP" : axi_interface.rresp,
|
||||
f"i_M_AXI_GP0_RDATA" : axi_interface.rdata,
|
||||
})
|
||||
|
||||
def add_i2c_emio(self, platform, i2c_name, i2c_number):
|
||||
ps7_i2c_pads = platform.request(i2c_name, i2c_number) #, loose=True)
|
||||
if ps7_i2c_pads is not None:
|
||||
o_i2c_scl = Signal()
|
||||
i_i2c_scl = Signal()
|
||||
t_i2c_scl = Signal()
|
||||
o_i2c_sda = Signal()
|
||||
i_i2c_sda = Signal()
|
||||
t_i2c_sda = Signal()
|
||||
|
||||
self.specials += Instance("IOBUF",
|
||||
i_T = t_i2c_sda,
|
||||
i_I = o_i2c_sda,
|
||||
io_IO = ps7_i2c_pads.sda,
|
||||
o_O = i_i2c_sda,
|
||||
)
|
||||
|
||||
self.specials += Instance("IOBUF",
|
||||
i_T = t_i2c_scl,
|
||||
i_I = o_i2c_scl,
|
||||
io_IO = ps7_i2c_pads.scl,
|
||||
o_O = i_i2c_scl,
|
||||
)
|
||||
|
||||
self.cpu_params.update({
|
||||
f"i_I2C{i2c_number}_SCL_I" : i_i2c_scl,
|
||||
f"o_I2C{i2c_number}_SCL_T" : t_i2c_scl,
|
||||
f"o_I2C{i2c_number}_SCL_O" : o_i2c_scl,
|
||||
|
||||
f"i_I2C{i2c_number}_SDA_I" : i_i2c_sda,
|
||||
f"o_I2C{i2c_number}_SDA_T" : t_i2c_sda,
|
||||
f"o_I2C{i2c_number}_SDA_O" : o_i2c_sda,
|
||||
})
|
||||
|
||||
def do_finalize(self):
|
||||
if len(self.ps7_tcl):
|
||||
self.ps7_tcl += [
|
||||
f"upgrade_ip [get_ips {self.ps7_name}]",
|
||||
f"generate_target all [get_ips {self.ps7_name}]",
|
||||
f"synth_ip [get_ips {self.ps7_name}]"
|
||||
]
|
||||
self.platform.toolchain.pre_synthesis_commands += self.ps7_tcl
|
||||
|
||||
self.specials += Instance(self.ps7_name, **self.cpu_params)
|
141
fast-servo/linien-gateware/cores/spi_phy.py
Normal file
141
fast-servo/linien-gateware/cores/spi_phy.py
Normal file
@ -0,0 +1,141 @@
|
||||
# This file is part of Fast Servo Software Package.
|
||||
#
|
||||
# Copyright (C) 2023 Jakub Matyas
|
||||
# Warsaw University of Technology <jakubk.m@gmail.com>
|
||||
# SPDX-License-Identifier: GPL-3.0-or-later
|
||||
#
|
||||
# This program is free software: you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation, either version 3 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <https://www.gnu.org/licenses/>.
|
||||
|
||||
from enum import Enum
|
||||
|
||||
from migen import *
|
||||
|
||||
|
||||
class SpiInterface(Enum):
|
||||
ADC = 0
|
||||
DAC = 1
|
||||
|
||||
|
||||
class SpiPhy(Module):
|
||||
def __init__(self, spi_type, ps7_spi_pads):
|
||||
assert isinstance(spi_type, SpiInterface)
|
||||
|
||||
self.ps_ss = Signal(3, reset_less=True)
|
||||
|
||||
self.ps_miso_o = Signal()
|
||||
self.ps_miso_t = Signal()
|
||||
self.ps_mosi_o = Signal()
|
||||
self.ps_mosi_t = Signal()
|
||||
self.ps_sclk_o = Signal()
|
||||
self.ps_sclk_t = Signal()
|
||||
self.ps_sclk_i = Signal()
|
||||
self.ps_mosi_i = Signal()
|
||||
self.ps_miso_i = Signal()
|
||||
self.ps_ss_i = Signal()
|
||||
self.ps_ss_t = Signal()
|
||||
|
||||
if spi_type.name == "ADC":
|
||||
|
||||
cs_translated = Signal(4, reset_less=True)
|
||||
|
||||
main_adc_miso = Signal(reset_less=True)
|
||||
aux_adc_miso_a = Signal(reset_less=True)
|
||||
aux_adc_miso_b = Signal(reset_less=True)
|
||||
aux_dac_miso = Signal(reset_less=True)
|
||||
|
||||
miso_signals = [main_adc_miso, aux_adc_miso_a, aux_adc_miso_b, aux_dac_miso]
|
||||
|
||||
# MAIN ADC
|
||||
self.specials += Instance("OBUFT", i_I=self.ps_sclk_o, i_T=self.ps_sclk_t, o_O=ps7_spi_pads.sclk)
|
||||
self.specials += Instance("OBUFT", i_I=self.ps_mosi_o, i_T=self.ps_mosi_t, o_O=ps7_spi_pads.mosi)
|
||||
self.specials += Instance("IBUF", i_I=ps7_spi_pads.miso, o_O=main_adc_miso)
|
||||
|
||||
# AUX ADC
|
||||
self.specials += Instance("OBUFT", i_I=self.ps_sclk_o, i_T=self.ps_sclk_t, o_O=ps7_spi_pads.aux_adc_sclk)
|
||||
self.specials += Instance("IBUF", i_I=ps7_spi_pads.aux_adc_miso_a, o_O=aux_adc_miso_a)
|
||||
self.specials += Instance("IBUF", i_I=ps7_spi_pads.aux_adc_miso_b, o_O=aux_adc_miso_b)
|
||||
|
||||
# AUX DAC
|
||||
self.specials += Instance("OBUFT", i_I=self.ps_sclk_o, i_T=self.ps_sclk_t, o_O=ps7_spi_pads.aux_dac_sclk)
|
||||
self.specials += Instance("OBUFT", i_I=self.ps_mosi_o, i_T=self.ps_mosi_t, o_O=ps7_spi_pads.aux_dac_mosi)
|
||||
self.specials += Instance("IBUF", i_I=ps7_spi_pads.aux_dac_miso, o_O=aux_dac_miso)
|
||||
|
||||
cases = {}
|
||||
# for i in range(4):
|
||||
# case_mask = ~(1 << i) & 0xF
|
||||
# print(f"Case mask: 0b{case_mask:04b}")
|
||||
# cases[i + 1] = [
|
||||
# cs_translated.eq(case_mask),
|
||||
# self.ps_miso_i.eq(miso_signals[i])
|
||||
# ]
|
||||
|
||||
cases[0b001] = [
|
||||
cs_translated.eq(0b1110),
|
||||
self.ps_miso_i.eq(main_adc_miso),
|
||||
]
|
||||
|
||||
cases[0b010] = [
|
||||
cs_translated.eq(0b1101),
|
||||
self.ps_miso_i.eq(aux_adc_miso_a),
|
||||
]
|
||||
|
||||
cases[0b011] = [
|
||||
cs_translated.eq(0b1011),
|
||||
self.ps_miso_i.eq(aux_adc_miso_b),
|
||||
]
|
||||
cases[0b100] = [
|
||||
cs_translated.eq(0b0111),
|
||||
self.ps_miso_i.eq(aux_dac_miso),
|
||||
]
|
||||
|
||||
cases["default"] = [
|
||||
cs_translated.eq(0b1111),
|
||||
self.ps_miso_i.eq(0b1),
|
||||
]
|
||||
|
||||
self.comb += [
|
||||
self.ps_ss_i.eq(1),
|
||||
Case(self.ps_ss, cases),
|
||||
|
||||
ps7_spi_pads.cs.eq(cs_translated[0]),
|
||||
|
||||
# only one CS line physically available to AUX ADC
|
||||
ps7_spi_pads.aux_adc_cs.eq(cs_translated[1] & cs_translated[2]),
|
||||
ps7_spi_pads.aux_dac_miso.eq(cs_translated[3]),
|
||||
|
||||
]
|
||||
else:
|
||||
self.specials += Instance(
|
||||
"spi2threewire",
|
||||
o_ps_sclk_i = self.ps_sclk_i,
|
||||
i_ps_sclk_o = self.ps_sclk_o,
|
||||
i_ps_sclk_t = self.ps_sclk_t,
|
||||
|
||||
o_ps_mosi_i = self.ps_mosi_i,
|
||||
i_ps_mosi_o = self.ps_mosi_o,
|
||||
i_ps_mosi_t = self.ps_mosi_t,
|
||||
|
||||
o_ps_miso_i = self.ps_miso_i,
|
||||
i_ps_miso_o = self.ps_miso_o,
|
||||
i_ps_miso_t = self.ps_miso_t,
|
||||
|
||||
o_ps_ss_i = self.ps_ss_i,
|
||||
i_ps_ss = self.ps_ss,
|
||||
i_ps_ss_t = self.ps_ss_t,
|
||||
|
||||
o_o_ss = ps7_spi_pads.cs,
|
||||
o_o_sclk = ps7_spi_pads.sclk,
|
||||
io_sdio = ps7_spi_pads.sdio,
|
||||
)
|
||||
|
336
fast-servo/linien-gateware/fast_servo_platform.py
Normal file
336
fast-servo/linien-gateware/fast_servo_platform.py
Normal file
@ -0,0 +1,336 @@
|
||||
# This file is part of Fast Servo Software Package.
|
||||
#
|
||||
# Copyright (C) 2022-2023 Jakub Matyas
|
||||
# Warsaw University of Technology <jakubk.m@gmail.com>
|
||||
# SPDX-License-Identifier: GPL-3.0-or-later
|
||||
#
|
||||
# This program is free software: you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation, either version 3 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <https://www.gnu.org/licenses/>.
|
||||
|
||||
from migen.build.generic_platform import *
|
||||
from migen.build.xilinx import XilinxPlatform
|
||||
|
||||
import os
|
||||
from fast_servo.gateware import verilog_dir
|
||||
|
||||
|
||||
# IOs ----------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
_io = [
|
||||
# Front panel LEDs
|
||||
("fp_led", 0, Pins("G7"), IOStandard("LVCMOS25")),
|
||||
("fp_led", 1, Pins("G8"), IOStandard("LVCMOS25")),
|
||||
("fp_led", 2, Pins("G2"), IOStandard("LVCMOS25")),
|
||||
("fp_led", 3, Pins("G3"), IOStandard("LVCMOS25")),
|
||||
|
||||
# LEDs
|
||||
("user_led", 0, Pins("AB16"), IOStandard("LVCMOS33")),
|
||||
("user_led", 1, Pins("AA14"), IOStandard("LVCMOS33")),
|
||||
("user_led", 2, Pins("AA15"), IOStandard("LVCMOS33")),
|
||||
|
||||
# ETH LEDs
|
||||
("eth_led", 0, Pins("V11"), IOStandard("LVCMOS33")),
|
||||
("eth_led", 1, Pins("U13"), IOStandard("LVCMOS33")),
|
||||
|
||||
("from_eth_phy", 0, Pins("J3"), IOStandard("LVCMOS18")),
|
||||
("from_eth_phy", 1, Pins("K8"), IOStandard("LVCMOS18")),
|
||||
|
||||
|
||||
# CLK 100 MHz from oscillator
|
||||
("clk100", 0, Pins("Y14"), IOStandard("LVCMOS33")),
|
||||
|
||||
# MGT clk from on-board Si5338A
|
||||
("mgt_clk1", 0,
|
||||
Subsignal("p", Pins("U5")),
|
||||
Subsignal("n", Pins("V5")),
|
||||
IOStandard("LVDS_25"),
|
||||
),
|
||||
|
||||
# FCLK125 from on-board Si5338A
|
||||
("fclk125", 0, Pins("K2"), IOStandard("LVCMOS18")),
|
||||
|
||||
# # ADC CLK
|
||||
# ("fpga_clk", 0,
|
||||
# Subsignal("p", Pins("C6")),
|
||||
# Subsignal("n", Pins("C5")),
|
||||
# IOStandard("LVDS_25"),
|
||||
# ),
|
||||
|
||||
# DAC CLK
|
||||
("fpga_clk", 1,
|
||||
Subsignal("p", Pins("J7")),
|
||||
Subsignal("n", Pins("J6")),
|
||||
IOStandard("LVDS_25"),
|
||||
),
|
||||
|
||||
# MAIN ADC LT2195
|
||||
("adc", 0,
|
||||
Subsignal("data0_p", Pins("F7 B7 E4 D1"), IOStandard("LVDS_25")),
|
||||
Subsignal("data0_n", Pins("E7 B6 E3 C1"), IOStandard("LVDS_25")),
|
||||
Subsignal("data1_p", Pins("A2 D5 F2 D7"), IOStandard("LVDS_25")),
|
||||
Subsignal("data1_n", Pins("A1 C4 F1 D6"), IOStandard("LVDS_25")),
|
||||
Subsignal("dco_p", Pins("B4"), IOStandard("LVDS_25")),
|
||||
Subsignal("dco_n", Pins("B3"), IOStandard("LVDS_25")),
|
||||
Subsignal("frame_p", Pins("B2"), IOStandard("LVDS_25")),
|
||||
Subsignal("frame_n", Pins("B1"), IOStandard("LVDS_25"))
|
||||
),
|
||||
|
||||
# ADC AFE
|
||||
("adc_afe", 0,
|
||||
Subsignal("ch1_gain", Pins("AA12"), IOStandard("LVCMOS33")),
|
||||
Subsignal("ch2_gain", Pins("AB11"), IOStandard("LVCMOS33")),
|
||||
Subsignal("nshdn_ch1", Pins("G4"), IOStandard("LVCMOS25")),
|
||||
Subsignal("nshdn_ch2", Pins("F4"), IOStandard("LVCMOS25")),
|
||||
),
|
||||
|
||||
# P5 R5 N1 N4 L2 P6 N3 R4 P1 L1 M3 M4 U2 T2
|
||||
# MAIN DAC AD9117
|
||||
("dac", 0,
|
||||
Subsignal("data",
|
||||
Pins("T2 U2 M4 M3 L1 P1 R4 N3 P6 L2 N4 N1 R5 P5"),
|
||||
IOStandard("LVCMOS18")),
|
||||
Subsignal("dclkio", Pins("U1"), IOStandard("LVCMOS18")),
|
||||
Subsignal("rst", Pins("T1"), IOStandard("LVCMOS18")),
|
||||
),
|
||||
|
||||
# DAC AFE
|
||||
("dac_afe", 0,
|
||||
Subsignal("ch1_pd_n", Pins("L5")),
|
||||
Subsignal("ch2_pd_n", Pins("L4")),
|
||||
IOStandard("LVCMOS18"),
|
||||
),
|
||||
|
||||
# AUXILIARY ADC
|
||||
("aux_adc", 0,
|
||||
Subsignal("diff_n", Pins("W18")),
|
||||
Subsignal("a", Pins("AB18 AB19 W17")),
|
||||
Subsignal("range", Pins("U19")),
|
||||
IOStandard("LVCMOS33")
|
||||
),
|
||||
|
||||
# AUXILIARY DAC
|
||||
("aux_dac", 0,
|
||||
Subsignal("nclr", Pins("V19")),
|
||||
Subsignal("bin", Pins("AA19")),
|
||||
Subsignal("nldac", Pins("AB21")),
|
||||
IOStandard("LVCMOS33")
|
||||
),
|
||||
|
||||
# ADC SPI
|
||||
("spi", 0,
|
||||
Subsignal("sclk", Pins("J1"), IOStandard("LVCMOS18")),
|
||||
Subsignal("mosi", Pins("J5"), IOStandard("LVCMOS18")),
|
||||
Subsignal("miso", Pins("K5"), IOStandard("LVCMOS18")),
|
||||
Subsignal("cs", Pins("J2"), IOStandard("LVCMOS18")),
|
||||
Subsignal("aux_adc_sclk", Pins("AB22"), IOStandard("LVCMOS33")),
|
||||
Subsignal("aux_adc_miso_a", Pins("Y18"), IOStandard("LVCMOS33")),
|
||||
Subsignal("aux_adc_miso_b", Pins("AA16"), IOStandard("LVCMOS33")),
|
||||
Subsignal("aux_adc_cs", Pins("Y19"), IOStandard("LVCMOS33")),
|
||||
Subsignal("aux_dac_sclk", Pins("V18"), IOStandard("LVCMOS33")),
|
||||
Subsignal("aux_dac_mosi", Pins("U17"), IOStandard("LVCMOS33")),
|
||||
Subsignal("aux_dac_miso", Pins("U18"), IOStandard("LVCMOS33")),
|
||||
Subsignal("aux_dac_cs", Pins("AA20"), IOStandard("LVCMOS33")),
|
||||
),
|
||||
|
||||
# DAC SPI
|
||||
("spi", 1,
|
||||
Subsignal("sclk", Pins("K3"), IOStandard("LVCMOS18")),
|
||||
Subsignal("sdio", Pins("R2"), IOStandard("LVCMOS18")),
|
||||
Subsignal("cs", Pins("R3"), IOStandard("LVCMOS18")),
|
||||
# Subsignal("sclk_aux", Pins("V18"), IOStandard("LVCMOS33")),
|
||||
# Subsignal("mosi_aux", Pins("U17"), IOStandard("LVCMOS33")),
|
||||
# Subsignal("miso_aux", Pins("U18"), IOStandard("LVCMOS33")),
|
||||
# Subsignal("cs_aux", Pins("AA20"), IOStandard("LVCMOS33")),
|
||||
),
|
||||
#Pins("Y15 AB14 AB13 V13 V14 V15 U12 W13 W12 R17 W15 AB17 Y12 Y13 V16 W16 AA17 Y17"),
|
||||
("gpio", 0,
|
||||
Subsignal("n", Pins("Y15 AB14 AB13 V13 V14 V15 U12 W13"), IOStandard("LVCMOS33")),
|
||||
Subsignal("p", Pins("W12 R17 W15 AB17 Y12 Y13 V16 W16"), IOStandard("LVCMOS33")),
|
||||
),
|
||||
|
||||
# PS7
|
||||
("ps7_clk", 0, Pins("_" * 1)),
|
||||
("ps7_porb", 0, Pins("_" * 1)),
|
||||
("ps7_srstb", 0, Pins("_" * 1)),
|
||||
("ps7_mio", 0, Pins("_" * 54)),
|
||||
("ps7_ddram", 0,
|
||||
Subsignal("addr", Pins("_" * 15)),
|
||||
Subsignal("ba", Pins("_" * 3)),
|
||||
Subsignal("cas_n", Pins("_" * 1)),
|
||||
Subsignal("ck_n", Pins("_" * 1)),
|
||||
Subsignal("ck_p", Pins("_" * 1)),
|
||||
Subsignal("cke", Pins("_" * 1)),
|
||||
Subsignal("cs_n", Pins("_" * 1)),
|
||||
Subsignal("dm", Pins("_" * 4)),
|
||||
Subsignal("dq", Pins("_" * 32)),
|
||||
Subsignal("dqs_n", Pins("_" * 4)),
|
||||
Subsignal("dqs_p", Pins("_" * 4)),
|
||||
Subsignal("odt", Pins("_" * 1)),
|
||||
Subsignal("ras_n", Pins("_" * 1)),
|
||||
Subsignal("reset_n", Pins("_" * 1)),
|
||||
Subsignal("we_n", Pins("_" * 1)),
|
||||
Subsignal("vrn", Pins("_" * 1)),
|
||||
Subsignal("vrp", Pins("_" * 1)),
|
||||
|
||||
),
|
||||
|
||||
# I2C0 to Si5340 on Fast Servo
|
||||
("ps7_i2c", 0,
|
||||
Subsignal("sda", Pins("M2")),
|
||||
Subsignal("scl", Pins("M1")),
|
||||
IOStandard("LVCMOS18")
|
||||
),
|
||||
|
||||
# Si540 nRST
|
||||
("nrst", 0, Pins("M7"), IOStandard("LVCMOS18")),
|
||||
|
||||
]
|
||||
|
||||
|
||||
|
||||
_connector_eem = [
|
||||
("eem", {
|
||||
"d0_cc_n": "C3",
|
||||
"d0_cc_p": "D3",
|
||||
"d1_n": "A4",
|
||||
"d1_p": "A5",
|
||||
"d2_n": "F6",
|
||||
"d2_p": "G6",
|
||||
"d3_n": "A6",
|
||||
"d3_p": "A7",
|
||||
"d4_n": "E5",
|
||||
"d4_p": "F5",
|
||||
"d5_n": "H3",
|
||||
"d5_p": "H4",
|
||||
"d6_n": "B8",
|
||||
"d6_p": "C8",
|
||||
"d7_n": "D8",
|
||||
"d7_p": "E8",
|
||||
}),
|
||||
]
|
||||
|
||||
_connector_gpio = [
|
||||
("gpio", {
|
||||
"qspi_io3": "Y15",
|
||||
"qspi_io2": "AB14",
|
||||
"qspi_io1": "AB13",
|
||||
"qspi_io0": "V13",
|
||||
"qspi_clk": "V14",
|
||||
"qspi_ncs": "V15",
|
||||
"hrtim_che1": "U12",
|
||||
"hrtim_che2": "W13",
|
||||
"hrtim_cha1": "W12",
|
||||
"hrtim_cha2": "R17",
|
||||
"lptim2_out": "W15",
|
||||
"uart4_tx": "AB17",
|
||||
"spi1_mosi": "Y12",
|
||||
"spi1_miso": "Y13",
|
||||
"spi1_nss": "V16",
|
||||
"spi1_sck": "W16",
|
||||
"i2c1_sda": "AA17",
|
||||
"i2c1_scl": "Y17",
|
||||
})
|
||||
]
|
||||
|
||||
# PS7 config ---------------------------------------------------------------------------------------
|
||||
|
||||
ps7_config_board_preset = {
|
||||
"PCW_PRESET_BANK0_VOLTAGE" : "LVCMOS 3.3V",
|
||||
"PCW_PRESET_BANK1_VOLTAGE" : "LVCMOS 1.8V",
|
||||
"PCW_CRYSTAL_PERIPHERAL_FREQMHZ" : "33.333333",
|
||||
"PCW_QSPI_PERIPHERAL_ENABLE" : "1",
|
||||
"PCW_QSPI_GRP_SINGLE_SS_ENABLE" : "1",
|
||||
"PCW_SINGLE_QSPI_DATA_MODE" : "x4",
|
||||
"PCW_QSPI_QSPI_IO" : "MIO 1 .. 6",
|
||||
"PCW_QSPI_GRP_FBCLK_ENABLE" : "1",
|
||||
|
||||
# SD Card
|
||||
"PCW_SD0_PERIPHERAL_ENABLE" : "1",
|
||||
"PCW_SD0_SD0_IO" : "MIO 40 .. 45",
|
||||
"PCW_MIO_40_PULLUP" : "disabled",
|
||||
"PCW_MIO_41_PULLUP" : "disabled",
|
||||
"PCW_MIO_42_PULLUP" : "disabled",
|
||||
"PCW_MIO_43_PULLUP" : "disabled",
|
||||
"PCW_MIO_44_PULLUP" : "disabled",
|
||||
"PCW_MIO_45_PULLUP" : "disabled",
|
||||
|
||||
# UART
|
||||
"PCW_UART0_PERIPHERAL_ENABLE" : "1",
|
||||
"PCW_UART0_UART0_IO" : "MIO 10 .. 11",
|
||||
|
||||
# ETHERNET
|
||||
"PCW_ACT_ENET0_PERIPHERAL_FREQMHZ" : "125",
|
||||
"PCW_ENET0_PERIPHERAL_CLKSRC" : "ARM PLL",
|
||||
"PCW_ENET0_PERIPHERAL_ENABLE" : "1",
|
||||
"PCW_ENET0_ENET0_IO" : "MIO 16 .. 27",
|
||||
"PCW_ENET0_GRP_MDIO_ENABLE" : "1",
|
||||
"PCW_ENET0_GRP_MDIO_IO" : "MIO 52 .. 53",
|
||||
"PCW_ENET_RESET_ENABLE" : "1",
|
||||
"PCW_ENET0_RESET_ENABLE" : "1",
|
||||
"PCW_ENET0_RESET_IO" : "MIO 50",
|
||||
|
||||
# USB
|
||||
"PCW_USB0_PERIPHERAL_ENABLE" : "1",
|
||||
"PCW_USB0_USB0_IO" : "MIO 28 .. 39",
|
||||
"PCW_USB_RESET_ENABLE" : "1",
|
||||
"PCW_USB0_RESET_ENABLE" : "1",
|
||||
"PCW_USB0_RESET_IO" : "MIO 51",
|
||||
|
||||
"PCW_WDT_PERIPHERAL_ENABLE" : "1",
|
||||
"PCW_TTC0_PERIPHERAL_ENABLE" : "1", # TTC0 required for Linux
|
||||
|
||||
# I2C
|
||||
"PCW_I2C_RESET_ENABLE" : "0",
|
||||
"PCW_I2C_RESET_POLARITY" : "Active Low",
|
||||
|
||||
# I2C0
|
||||
"PCW_I2C0_I2C0_IO" : "EMIO",
|
||||
"PCW_I2C0_PERIPHERAL_ENABLE" : "1",
|
||||
"PCW_I2C0_GRP_INT_ENABLE" : "1",
|
||||
"PCW_I2C0_GRP_INT_IO" : "EMIO",
|
||||
|
||||
# I2C1
|
||||
"PCW_I2C1_PERIPHERAL_ENABLE" : "1",
|
||||
"PCW_I2C1_I2C1_IO" : "MIO 48 .. 49",
|
||||
"PCW_I2C1_I2C1_IO" : "MIO 12 .. 13",
|
||||
"PCW_I2C1_PERIPHERAL_ENABLE" : "1",
|
||||
|
||||
"PCW_UIPARAM_DDR_MEMORY_TYPE" : "DDR 3 (Low Voltage)",
|
||||
"PCW_UIPARAM_DDR_PARTNO" : "MT41J256M16 RE-125",
|
||||
"PCW_GPIO_MIO_GPIO_ENABLE" : "1",
|
||||
|
||||
"PCW_FPGA0_PERIPHERAL_FREQMHZ" : "100",
|
||||
"PCW_EN_CLK0_PORT" : "0", # dont use FCLK0
|
||||
}
|
||||
|
||||
class Platform(XilinxPlatform):
|
||||
default_clk_name = "clk100"
|
||||
default_clk_period = 10.0
|
||||
|
||||
def __init__(self):
|
||||
XilinxPlatform.__init__(self, "xc7z015-clg485-1", _io, _connector_gpio + _connector_eem, toolchain="vivado")
|
||||
ps7_config = ps7_config_board_preset
|
||||
self.ps7_config = ps7_config
|
||||
|
||||
verilog_sources = os.listdir(verilog_dir)
|
||||
self.add_sources(verilog_dir, *verilog_sources)
|
||||
|
||||
def do_finalize(self, fragment):
|
||||
try:
|
||||
XilinxPlatform.do_finalize(self, fragment)
|
||||
self.add_period_constraint(self.lookup_request(self.default_clk_name, loose=True), self.default_clk_period)
|
||||
except ValueError:
|
||||
pass
|
||||
except ConstraintError:
|
||||
pass
|
290
fast-servo/linien-gateware/fast_servo_soc.py
Normal file
290
fast-servo/linien-gateware/fast_servo_soc.py
Normal file
@ -0,0 +1,290 @@
|
||||
# This file is part of Fast Servo Software Package.
|
||||
#
|
||||
# Copyright (C) 2023 Jakub Matyas
|
||||
# Warsaw University of Technology <jakubk.m@gmail.com>
|
||||
# SPDX-License-Identifier: GPL-3.0-or-later
|
||||
#
|
||||
# This program is free software: you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation, either version 3 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <https://www.gnu.org/licenses/>.
|
||||
|
||||
import os
|
||||
|
||||
from migen import *
|
||||
from misoc.interconnect import csr_bus
|
||||
from misoc.interconnect.csr import AutoCSR, CSRStorage
|
||||
|
||||
from fast_servo.gateware.cores.adc import ADC, AUX_ADC_CTRL
|
||||
from fast_servo.gateware.cores.dac import AUX_DAC_CTRL, DAC
|
||||
from fast_servo.gateware.cores.pitaya_ps import Axi2Sys, Sys2CSR, SysCDC, SysInterconnect
|
||||
from fast_servo.gateware.cores.ps7 import PS7
|
||||
from fast_servo.gateware.cores.spi_phy import SpiInterface, SpiPhy
|
||||
|
||||
|
||||
class CRG(Module):
|
||||
def __init__(self, platform):
|
||||
self.ps_rst = Signal()
|
||||
self.locked = Signal()
|
||||
self.clock_domains.cd_sys = ClockDomain()
|
||||
self.clock_domains.cd_sys_double = ClockDomain()
|
||||
self.clock_domains.cd_idelay = ClockDomain()
|
||||
|
||||
# # #
|
||||
|
||||
# Clk.
|
||||
clk100 = platform.request("clk100")
|
||||
platform.add_period_constraint(clk100, 10.0)
|
||||
self.clkin = clk100
|
||||
clk100_buf = Signal()
|
||||
self.specials += Instance("IBUFG", i_I=clk100, o_O=clk100_buf)
|
||||
|
||||
clk_feedback = Signal()
|
||||
clk_feedback_buf = Signal()
|
||||
|
||||
clk_sys = Signal()
|
||||
clk_idelay = Signal()
|
||||
|
||||
self.specials += [
|
||||
Instance(
|
||||
"PLLE2_BASE",
|
||||
p_BANDWIDTH="OPTIMIZED",
|
||||
p_DIVCLK_DIVIDE=1,
|
||||
p_CLKFBOUT_PHASE=0.0,
|
||||
p_CLKFBOUT_MULT=10,
|
||||
p_CLKIN1_PERIOD=10.0,
|
||||
p_REF_JITTER1=0.01,
|
||||
p_STARTUP_WAIT="FALSE",
|
||||
i_CLKIN1=clk100_buf,
|
||||
i_PWRDWN=0,
|
||||
i_RST=self.ps_rst,
|
||||
i_CLKFBIN=clk_feedback_buf,
|
||||
o_CLKFBOUT=clk_feedback,
|
||||
p_CLKOUT0_DIVIDE=10,
|
||||
p_CLKOUT0_PHASE=0.0,
|
||||
p_CLKOUT0_DUTY_CYCLE=0.5,
|
||||
o_CLKOUT0=clk_sys, # 100 MHz <- sys_clk
|
||||
p_CLKOUT1_DIVIDE=5,
|
||||
p_CLKOUT1_PHASE=0.0,
|
||||
p_CLKOUT1_DUTY_CYCLE=0.5,
|
||||
o_CLKOUT1=clk_idelay, # 200 MHZ <- 2 * sys_clk = 2*100 MHz
|
||||
o_LOCKED=self.locked,
|
||||
)
|
||||
]
|
||||
|
||||
self.specials += Instance("BUFG", i_I=clk_feedback, o_O=clk_feedback_buf)
|
||||
self.specials += Instance("BUFG", i_I=clk_sys, o_O=self.cd_sys.clk)
|
||||
self.specials += Instance("BUFG", i_I=clk_idelay, o_O=self.cd_idelay.clk)
|
||||
self.specials += Instance( |