esavkin
/
zynq-rs
forked from M-Labs/zynq-rs
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

GIC: fix wrong core target config when enabling interrupt (#109) 

# Summary

- Before the patch, an extra 1 is added to `target_cpu` and the interrupt will be configured to the wrong CPU target.

| target_cpu | bits set before patch | bits set after patch   |
| -----------| -----------                      | -----------                       |
| core0      | 0b10 (enable interrupt on core1) | 0b01 (enable interrupt on core0)  |
| core1      | 0b11 (enable interrupt on core0 & core1)| 0b10 (enable interrupt on core1) |

- [Correct ICDIPTR Register configuration from AMD](https://docs.xilinx.com/r/en-US/ug585-zynq-7000-SoC-TRM/Software-Generated-Interrupts-SGI?tocId=0TsxAmy8MHRPDsayG96K1Q)

Reviewed-on: M-Labs/zynq-rs#109
Co-authored-by: morgan <mc@m-labs.hk>
Co-committed-by: morgan <mc@m-labs.hk>
This commit is contained in:
morgan 2023-12-19 18:41:03 +08:00 committed by sb10q
parent a43b8bf64e
commit 4168eb63a7
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
libboard_zynq/src/gic.rs
View File

@ -115,7 +115,7 @@ impl InterruptController {
let m = (id.0 >> 2) as usize; let m = (id.0 >> 2) as usize;
let n = (8 * (id.0 & 3)) as usize; let n = (8 * (id.0 & 3)) as usize;
unsafe { unsafe {
self.mpcore.icdiptr[m].modify(|mut icdiptr| *icdiptr.set_bits(n..=n+1, target_cpu as u32 + 1)); self.mpcore.icdiptr[m].modify(|mut icdiptr| *icdiptr.set_bits(n..=n+1, target_cpu as u32));
} }
// sensitivity // sensitivity