dsleung
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  • Joined on 2020-05-28
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dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-07-24 12:55:23 +08:00
dec39cb11d Re-add MUL instruction
dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-07-24 12:49:40 +08:00
f33d229b2c Fix XOR instruction
dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-07-24 12:48:15 +08:00
d54269d3f0 Fix SUB instruction
dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-07-24 12:46:32 +08:00
fe2ff5150a Fix SRL instruction
dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-07-24 12:44:53 +08:00
6d35ecdc80 Fix SRA instruction
dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-07-24 12:42:42 +08:00
3c1510ebbc Fix SLT instruction
dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-07-24 12:40:37 +08:00
18e43d9689 Fix SLL instruction
dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-07-24 12:33:08 +08:00
d59ebda628 Fix OR instruction
dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-07-24 12:24:51 +08:00
3028246b73 Fix AND instruction
dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-07-24 12:21:17 +08:00
eedfc843f7 Fix ADD instruction
dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-07-24 12:17:11 +08:00
73005eb3c3 Revert MUL instruction
dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-07-24 12:13:50 +08:00
14c87fdde2 Add MUL instruction for RV32M
dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-07-23 14:33:50 +08:00
35a53071aa Complete generator for RV32I ISA
dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-07-23 12:57:48 +08:00
2e7cc106aa Add missing return in ports in RV32I ISA
dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-07-23 12:43:12 +08:00
badd480a45 Prepare generator script for RV32I ISA
dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-07-23 11:18:51 +08:00
d54a60879d Add list of supported instructions for RV32I
dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-07-22 16:44:59 +08:00
41f01f22a8 Update README.md
dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-07-22 16:39:18 +08:00
61393b9a4f Add AND instruction for RV32I
dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-07-22 16:36:51 +08:00
93978ccdb4 Add OR instruction for RV32I
dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-07-22 16:33:00 +08:00
4eae7064fb Add SRA instruction for RV32I