dsleung

dsleung pushed to restructuring at M-Labs/riscv-formal-nmigen

2020-08-07 12:54:43 +08:00

2e2300e5c8 Update insns/README.md

dsleung pushed to restructuring at M-Labs/riscv-formal-nmigen

2020-08-07 12:29:07 +08:00

a8cf15e123 Add generic instruction class

dsleung pushed to restructuring at M-Labs/riscv-formal-nmigen

2020-08-06 16:45:05 +08:00

56048099b3 Correct typo in insns/README.md

dsleung pushed to restructuring at M-Labs/riscv-formal-nmigen

2020-08-06 14:46:12 +08:00

9a3cb8e88a Fix table formatting in insns/README.md

dsleung pushed to restructuring at M-Labs/riscv-formal-nmigen

2020-08-06 14:13:09 +08:00

7c420cce7a Categorize all (to be) supported instructions

dsleung pushed to restructuring at M-Labs/riscv-formal-nmigen

2020-08-06 12:36:12 +08:00

3eaed129c2 Begin re-organization of project structure

dsleung pushed to restructuring at M-Labs/riscv-formal-nmigen

2020-08-06 12:25:51 +08:00

dsleung deleted branch feature/refactor-insns from M-Labs/riscv-formal-nmigen

2020-08-06 09:47:43 +08:00

dsleung merged pull request M-Labs/riscv-formal-nmigen#1

2020-08-06 09:47:30 +08:00

Refactor supported instructions to improve code reuse

dsleung pushed to master at M-Labs/riscv-formal-nmigen

2020-08-06 09:47:30 +08:00

1d315b4735 Merge pull request 'Refactor supported instructions to improve code reuse' (#1) from feature/refactor-insns into master

7c60451bfa Add README for instructions

c4e30e9c55 Add REMU instruction

af8704cea0 Add REM instruction

78fb149761 Add DIVU instruction

Compare 85 commits »

dsleung created pull request M-Labs/riscv-formal-nmigen#1

2020-08-05 12:57:56 +08:00

Refactor supported instructions to improve code reuse

dsleung pushed to feature/refactor-insns at M-Labs/riscv-formal-nmigen

2020-08-05 12:54:55 +08:00

7c60451bfa Add README for instructions

dsleung pushed to feature/refactor-insns at M-Labs/riscv-formal-nmigen

2020-08-04 17:17:45 +08:00

c4e30e9c55 Add REMU instruction

dsleung pushed to feature/refactor-insns at M-Labs/riscv-formal-nmigen

2020-08-04 17:14:57 +08:00

af8704cea0 Add REM instruction

dsleung pushed to feature/refactor-insns at M-Labs/riscv-formal-nmigen

2020-08-04 17:12:24 +08:00

78fb149761 Add DIVU instruction

dsleung pushed to feature/refactor-insns at M-Labs/riscv-formal-nmigen

2020-08-04 17:09:29 +08:00

2a809073a5 Add DIV instruction

dsleung pushed to feature/refactor-insns at M-Labs/riscv-formal-nmigen

2020-08-04 17:06:56 +08:00

7b39ce135f Add MULHU instruction

dsleung pushed to feature/refactor-insns at M-Labs/riscv-formal-nmigen

2020-08-04 17:04:11 +08:00

ee38e3a61d Add MULHSU instruction

dsleung pushed to feature/refactor-insns at M-Labs/riscv-formal-nmigen

2020-08-04 17:00:51 +08:00

a26813835f Add MULH instruction

dsleung pushed to feature/refactor-insns at M-Labs/riscv-formal-nmigen

2020-08-04 16:57:52 +08:00

e1bbf567c2 Add MUL instruction