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f76e9321d7
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armv7-none-eabihf.json: forbid unaligned access
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2020-06-22 00:35:27 +02:00 |
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875bc74df9
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libcortex_a9: implement pl310 l2cache
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2020-06-20 02:25:07 +02:00 |
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b33ccf83ba
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eth: doc
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2020-06-18 18:07:50 +02:00 |
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b4bcc6cf5c
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TcpStream: add send_slice()
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2020-06-18 01:56:49 +02:00 |
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a80a2c67ef
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eth: put desc list behind UncachedSlice, invalidate buffers, add barriers
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2020-06-18 01:28:29 +02:00 |
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d96343c249
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uncached: refactor into UncachedSlice
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2020-06-18 01:28:25 +02:00 |
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ae739146c5
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cache: add the required barriers
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2020-06-18 01:27:34 +02:00 |
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f50018092c
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mmu: add early memory barrier to L1Table.update()
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2020-06-18 01:27:34 +02:00 |
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7c4d390ce4
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libcortex_a9: start Uncached
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2020-06-18 01:27:34 +02:00 |
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6761575b30
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mmu: add L1Table.update()
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2020-06-18 01:27:34 +02:00 |
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aebce435e2
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mmu: switch bufferable=1 (writeback) for DDR pages
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2020-06-18 01:27:34 +02:00 |
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98f5099684
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removed newline character
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2020-06-16 17:36:01 +08:00 |
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2c3fa991ad
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implemented display trait for errors
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2020-06-16 17:36:01 +08:00 |
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2c14a2a1a2
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fixed global timer reset
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2020-06-16 17:31:37 +08:00 |
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191da7c959
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Added Copy trait for Milliseconds struct.
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2020-06-16 14:56:29 +08:00 |
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d52466cacf
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DevC driver refactored.
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2020-06-16 14:55:53 +08:00 |
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a17a5d2925
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sdcard: Changed some debug to trace.
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2020-06-15 16:54:30 +08:00 |
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e0f26871db
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devc working!
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2020-06-15 16:07:31 +08:00 |
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82ec1ba7a7
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sdio: better logging
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2020-06-13 16:31:25 +08:00 |
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d3b488bfb3
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standard capacity support
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2020-06-11 10:21:01 +08:00 |
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074b3547de
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sdio: fix unsound MaybeUninit usage
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2020-06-11 10:07:19 +08:00 |
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316ea61702
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sdio: move ADMA2_DESCR32_TABLE into SdCard
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2020-06-11 10:07:19 +08:00 |
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1586190712
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sdio: turn Adma2Desc32.attribute into a register!
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2020-06-11 10:07:19 +08:00 |
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32349e9dec
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sdio: convert Adma2Desc32 to VolatileCells, make ADMA2_DESCR32_TABLE: MaybeUninit
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2020-06-11 10:07:19 +08:00 |
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b942cdcbc8
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sdio: change Adma2Desc32 alignment from 1 to 4
this should not break anything.
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2020-06-11 10:07:19 +08:00 |
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a1a211334f
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eth: always just allocate desc list + buffers
buffers are allocated vec anyway. this removes the lifetime hack and
further prepares work on cache-line alignment to enable L1 writeback.
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2020-06-11 00:21:18 +02:00 |
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187ef703f2
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experiments: use stream.close() instead of .flush()
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2020-06-10 20:21:01 +02:00 |
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cf17a1c60a
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removed unneeded methods
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2020-06-10 12:55:22 +08:00 |
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5332587de6
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Changed mutability
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2020-06-10 12:54:50 +08:00 |
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0ebc4a61c8
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Modified SDIO to handle u8 buffer instead of u32.
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2020-06-09 17:03:17 +08:00 |
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40d5eb8232
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fixed compilation error
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2020-06-05 12:27:41 +08:00 |
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d01d0f69a4
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formatting commit
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2020-06-05 12:27:19 +08:00 |
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236592ae66
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SDIO module completed
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2020-06-05 12:27:12 +08:00 |
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a53ed8acc8
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add remote run script
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2020-06-04 19:57:52 +08:00 |
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7695d6d8df
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openocd: fix cora z7-10 PL_TAPID
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2020-05-16 01:34:09 +02:00 |
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2c82fb793e
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Merge pull request 'sdio-registers' (#29)
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2020-05-15 06:44:32 +08:00 |
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0c48dd934e
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libboard_zynq: fix sclr::ddriob_ddr_ctrl vref_int_en
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2020-05-10 22:14:55 +02:00 |
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3841accd9c
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libboard_zynq: fix ddr memtest range
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2020-05-09 02:53:58 +02:00 |
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3e02980c20
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libboard_zynq: fix access to "full" 1022 MB on target_zc706
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2020-05-09 02:35:39 +02:00 |
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66cd0c7630
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libcortex_a9: allow access for full 1GB of DDR
|
2020-05-09 02:35:39 +02:00 |
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4e1f46b3e2
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core1: support redirecting vectors to sdram
|
2020-05-06 22:07:12 +08:00 |
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73b0ec9837
|
fixed typo
|
2020-05-06 13:58:46 +08:00 |
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4acee21c05
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Merge branch 'master' of git.m-labs.hk:M-Labs/zc706 into sdio-registers
|
2020-05-06 11:06:38 +08:00 |
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ce844f1b02
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devc: add is_done()
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2020-05-04 22:16:53 +08:00 |
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60e996a121
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update cargoSha256
|
2020-05-03 09:58:58 +08:00 |
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27094da9ff
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nix: disable post-installation fixup on ARM binaries
|
2020-05-03 09:47:58 +08:00 |
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c955eaae7f
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libboard_zynq: flush Uart by waiting for tx idle
|
2020-05-02 23:32:01 +02:00 |
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0f666c570c
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libboard_zynq: remove unneeded Uart flush
|
2020-05-02 23:30:45 +02:00 |
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244ccdeac2
|
finished register definitions
|
2020-05-01 15:38:07 +08:00 |
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e047c2900b
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ddr: log clock info with debug level
|
2020-05-01 12:27:43 +08:00 |
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