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libcortex_a9/mutex: use AcqRel for CAS operations

master
pca006132 2020-08-24 15:24:20 +08:00
parent bb09d25378
commit c13ca614ef
1 changed files with 3 additions and 6 deletions
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9
libcortex_a9/src/mutex.rs
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@ -3,7 +3,7 @@ use core::sync::atomic::{AtomicU32, Ordering};
use core::cell::UnsafeCell; use core::cell::UnsafeCell;
use super::{ use super::{
spin_lock_yield, notify_spin_lock, spin_lock_yield, notify_spin_lock,
asm::{dmb, enter_critical, exit_critical} asm::{enter_critical, exit_critical}
}; };
const LOCKED: u32 = 1; const LOCKED: u32 = 1;
@ -32,30 +32,27 @@ impl<T> Mutex<T> {
/// Lock the Mutex, blocks when already locked /// Lock the Mutex, blocks when already locked
pub fn lock(&self) -> MutexGuard<T> { pub fn lock(&self) -> MutexGuard<T> {
let mut irq = unsafe { enter_critical() }; let mut irq = unsafe { enter_critical() };
while self.locked.compare_and_swap(UNLOCKED, LOCKED, Ordering::Acquire) != UNLOCKED { while self.locked.compare_and_swap(UNLOCKED, LOCKED, Ordering::AcqRel) != UNLOCKED {
unsafe { unsafe {
exit_critical(irq); exit_critical(irq);
spin_lock_yield(); spin_lock_yield();
irq = enter_critical(); irq = enter_critical();
} }
} }
dmb();
MutexGuard { mutex: self, irq } MutexGuard { mutex: self, irq }
} }
pub fn try_lock(&self) -> Option<MutexGuard<T>> { pub fn try_lock(&self) -> Option<MutexGuard<T>> {
let irq = unsafe { enter_critical() }; let irq = unsafe { enter_critical() };
if self.locked.compare_and_swap(UNLOCKED, LOCKED, Ordering::Acquire) != UNLOCKED { if self.locked.compare_and_swap(UNLOCKED, LOCKED, Ordering::AcqRel) != UNLOCKED {
unsafe { exit_critical(irq) }; unsafe { exit_critical(irq) };
None None
} else { } else {
dmb();
Some(MutexGuard { mutex: self, irq }) Some(MutexGuard { mutex: self, irq })
} }
} }
fn unlock(&self) { fn unlock(&self) {
dmb();
self.locked.store(UNLOCKED, Ordering::Release); self.locked.store(UNLOCKED, Ordering::Release);
notify_spin_lock(); notify_spin_lock();