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7 changed files with 170 additions and 2 deletions

16
Cargo.lock generated
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@ -107,6 +107,22 @@ dependencies = [
"volatile-register", "volatile-register",
] ]
[[package]]
name = "libboard_zynq_us"
version = "0.0.0"
dependencies = [
"bit_field",
"embedded-hal",
"libasync",
"libboard_zynq",
"libregister",
"log",
"nb 0.1.3",
"smoltcp",
"void",
"volatile-register",
]
[[package]] [[package]]
name = "libconfig" name = "libconfig"
version = "0.1.0" version = "0.1.0"

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@ -8,6 +8,7 @@ members = [
"libconfig", "libconfig",
"experiments", "experiments",
"szl", "szl",
"libboard_zynq_us",
] ]
[profile.release] [profile.release]

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@ -5,8 +5,8 @@ use libregister::*;
use super::slcr; use super::slcr;
use super::clocks::Clocks; use super::clocks::Clocks;
mod regs; pub mod regs;
mod baud_rate_gen; pub mod baud_rate_gen;
pub struct Uart { pub struct Uart {
regs: &'static mut regs::RegisterBlock, regs: &'static mut regs::RegisterBlock,

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@ -0,0 +1,28 @@
[package]
name = "libboard_zynq_us"
description = "Drivers for peripherals in the Zynq UltraScale+ PS"
version = "0.0.0"
authors = ["M-Labs"]
edition = "2018"
[features]
target_zcu111 = []
ipv6 = [ "smoltcp/proto-ipv6" ]
default = [ "target_zcu111" ]
[dependencies]
volatile-register = "0.2"
bit_field = "0.10"
embedded-hal = "0.2"
nb = "0.1"
void = { version = "1", default-features = false }
log = "0.4"
libregister = { path = "../libregister" }
# libcortex_a9 = { path = "../libcortex_a9" }
libasync = { path = "../libasync" }
libboard_zynq = { path = "../libboard_zynq" }
[dependencies.smoltcp]
version = "0.7"
features = ["ethernet", "proto-ipv4", "socket-tcp"]
default-features = false

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@ -0,0 +1,102 @@
///! FPD clock and reset control
use volatile_register::{RO, RW, WO};
use libregister::{
register, register_at,
register_bit, register_bits,
};
#[repr(C)]
pub struct RegisterBlock {
// CRF_APB
pub err_ctrl: RW<u32>,
pub ir_status: RW<u32>, // todo: WTC LSB
pub ir_mask: RO<u32>,
pub ir_enable: WO<u32>,
pub ir_disable: WO<u32>,
pub crf_wprot: RW<u32>,
pub apll_ctrl: PllCtrl,
pub apll_cfg: PllCfg,
pub apll_frac_cfg: PllFracCfg,
pub dpll_ctrl: PllCtrl,
pub dpll_cfg: PllCfg,
pub dpll_frac_cfg: PllFracCfg,
pub vpll_ctr: PllCtrl,
pub vpll_cfg: PllCfg,
pub vpll_frac_cfg: PllFracCfg,
pub pll_status: PllStatus,
pub apll_to_lpd_ctrl: PllToLpdCtrl,
pub dpll_to_lpd_ctrl: PllToLpdCtrl,
pub vpll_to_lpd_ctrl: PllToLpdCtrl,
reserved1: [u32; 3],
pub apu_clk_ctrl: ApuClkCtrl,
pub dbg_trace_clk_ctrl: RW<u32>,
pub dbg_fpd_clk_ctrl: RW<u32>,
reserved2: [u32; 1],
pub dp_video_clk_ctrl: RW<u32>,
pub dp_audio_clk_ctrl: RW<u32>,
reserved3: [u32; 1],
pub dp_sys_clk_ctrl: RW<u32>,
pub ddr_clk_ctrl: DdrClkCtrl,
pub gpu_clk_ctrl: RW<u32>,
reserved4: [u32; 6],
pub sata_clk_ctrl: RW<u32>,
reserved5: [u32; 4],
pub pcie_clk_ctrl: RW<u32>,
pub fpd_dma_clk_ctrl: RW<u32>,
pub dp_dma_clk_ctrl: RW<u32>,
pub topsw_main_clk_ctrl: RW<u32>,
pub topsw_lsbus_clk_ctrl: RW<u32>,
reserved6: [u32; 8],
pub dbg_tstmp_clk_ctrl: RW<u32>,
reserved7: [u32; 1],
pub rst_fpd_top: RW<u32>,
pub rst_fpd_apu: RW<u32>,
pub rst_ddr_ss: RW<u32>,
}
register_at!(RegisterBlock, 0xFD1A_0000, crf_apb);
register!(pll_ctrl, PllCtrl, RW, u32);
register_bits!(pll_ctrl, post_src, u8, 24, 26);
register_bits!(pll_ctrl, pre_src, u8, 20, 22);
register_bit!(pll_ctrl, div2, 16);
register_bits!(pll_ctrl, fbdiv, u8, 8, 14);
register_bit!(pll_ctrl, bypass, 3);
register_bit!(pll_ctrl, reset, 0);
register!(pll_cfg, PllCfg, RW, u32);
register_bits!(pll_cfg, lock_dly, u8, 25, 31);
register_bits!(pll_cfg, lock_cnt, u16, 13, 22);
register_bits!(pll_cfg, lfhf, u8, 10, 11);
register_bits!(pll_cfg, cp, u8, 5, 8);
register_bits!(pll_cfg, res, u8, 0, 3);
register!(pll_frac_cfg, PllFracCfg, RW, u32);
register_bit!(pll_frac_cfg, enabled, 31);
register_bits!(pll_frac_cfg, data, u16, 0, 15);
register!(pll_status, PllStatus, RO, u32);
register_bit!(pll_status, vpll_stable, 5);
register_bit!(pll_status, dpll_stable, 4);
register_bit!(pll_status, apll_stable, 3);
register_bit!(pll_status, vpll_lock, 2);
register_bit!(pll_status, dpll_lock, 1);
register_bit!(pll_status, apll_lock, 0);
register!(pll_to_lpd_ctrl, PllToLpdCtrl, RW, u32);
register_bits!(pll_to_lpd_ctrl, divisor0, u8, 8, 13);
register!(apu_clk_ctrl, ApuClkCtrl, RW, u32);
register_bit!(apu_clk_ctrl, clkact_half, 25);
register_bit!(apu_clk_ctrl, clkact_full, 24);
register_bits!(apu_clk_ctrl, divisor0, u8, 8, 13);
// 000: APLL
// 010: DPLL
// 011: VPLL
register_bits!(apu_clk_ctrl, srcsel, u8, 0, 2);
register!(ddr_clk_ctrl, DdrClkCtrl, RW, u32);
register_bits!(ddr_clk_ctrl, divisor0, u8, 8, 13);
// 000: DPLL
// 001: VPLL
register_bits!(ddr_clk_ctrl, srcsel, u8, 0, 2);

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@ -0,0 +1,14 @@
///! Register definitions for UltraScale+ System Level Control
pub mod crf_apb;
// APU
// FPD_SLCR
// FPD_SLCR_SECURE
// IOU_SLCR
// IOU_SECURE_SLCR
// IOU_SCNTRS
// LPD_SLCR
// LPD_SLCR_SECURE
// CRL_APB
// RPU
// CCI_GPV
// FPD_GPV

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@ -0,0 +1,7 @@
use libregister::register_at;
use libboard_zynq::uart::baud_rate_gen;
use libboard_zync::uart::regs::RegisterBlock;
register_at!(RegisterBlock, 0xFF000000, uart0);
register_at!(RegisterBlock, 0xFF010000, uart1); // note: PS_UART1 is not connected on ZCU111