bradbqc
/
zynq-rs
forked from M-Labs/zynq-rs
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

libboard_zynq: add ps7_init for cora_z7_10

esavkin/reboot_support
Astro 2020-11-08 19:28:59 +01:00
parent aef010cb14
commit e508b78b3e
4 changed files with 3993 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
experiments/src/main.rs
View File

@ -145,6 +145,8 @@ pub fn main_core0() {
let timer = libboard_zynq::timer::GlobalTimer::start(); let timer = libboard_zynq::timer::GlobalTimer::start();
let mut ddr = zynq::ddr::DdrRam::ddrram(); let mut ddr = zynq::ddr::DdrRam::ddrram();
// ddr init may call ps7_init, reconfiguring the uart
libboard_zynq::stdio::drop_uart();
#[cfg(not(feature = "target_zc706"))] #[cfg(not(feature = "target_zc706"))]
ddr.memtest(); ddr.memtest();
ram::init_alloc_ddr(&mut ddr); ram::init_alloc_ddr(&mut ddr);

6
libboard_zynq/src/ddr/mod.rs
View File

@ -4,7 +4,7 @@ use crate::{print, println};
use super::slcr::{self, DdriobVrefSel}; use super::slcr::{self, DdriobVrefSel};
use super::clocks::{Clocks, source::{DdrPll, ClockSource}}; use super::clocks::{Clocks, source::{DdrPll, ClockSource}};
#[cfg(feature = "target_redpitaya")] #[cfg(any(feature = "target_redpitaya", feature = "target_cora_z7_10"))]
use super::ps7_init; use super::ps7_init;
mod regs; mod regs;
@ -30,11 +30,11 @@ pub struct DdrRam {
impl DdrRam { impl DdrRam {
pub fn ddrram() -> Self { pub fn ddrram() -> Self {
if cfg!(feature = "target_redpitaya") { if cfg!(any(feature = "target_redpitaya", feature = "target_cora_z7_10")) {
// We have not yet fixed red pitaya initialization yet. It seems // We have not yet fixed red pitaya initialization yet. It seems
// that the clock configuration, iob settings and ddr settings are // that the clock configuration, iob settings and ddr settings are
// all problematic // all problematic
#[cfg(feature = "target_redpitaya")] #[cfg(any(feature = "target_redpitaya", feature = "target_cora_z7_10"))]
ps7_init::apply(); ps7_init::apply();
let regs = regs::RegisterBlock::ddrc(); let regs = regs::RegisterBlock::ddrc();
DdrRam { regs } DdrRam { regs }

3982
libboard_zynq/src/ps7_init/cora_z7_10.rs Normal file
View File

File diff suppressed because it is too large Load Diff

8
libboard_zynq/src/ps7_init/mod.rs
View File

@ -5,14 +5,18 @@ use crate::println;
mod zc706; mod zc706;
#[cfg(feature = "target_redpitaya")] #[cfg(feature = "target_redpitaya")]
mod redpitaya; mod redpitaya;
#[cfg(not(any(feature = "target_zc706", feature = "target_redpitaya")))] #[cfg(feature = "target_cora_z7_10")]
mod cora_z7_10;
#[cfg(not(any(feature = "target_zc706", feature = "target_redpitaya", feature = "target_cora_z7_10")))]
mod none; mod none;
#[cfg(feature = "target_zc706")] #[cfg(feature = "target_zc706")]
use zc706 as target; use zc706 as target;
#[cfg(feature = "target_redpitaya")] #[cfg(feature = "target_redpitaya")]
use redpitaya as target; use redpitaya as target;
#[cfg(not(any(feature = "target_zc706", feature = "target_redpitaya")))] #[cfg(feature = "target_cora_z7_10")]
use cora_z7_10 as target;
#[cfg(not(any(feature = "target_zc706", feature = "target_redpitaya", feature = "target_cora_z7_10")))]
use none as target; use none as target;
pub fn report_differences() { pub fn report_differences() {