- Dresden
- https://spaceboyz.net/~astro/
- Joined on
2019-04-18
5695977531
Revert "artiq-board.nix: move compilers into nativeBuildInputs"
2e62831998
Revert "artiq-fast: add strictDeps=true to fetchcargo.nix"
fd25af0733
artiq-board.nix: move compilers into nativeBuildInputs
843da12452
artiq-fast: add strictDeps=true to fetchcargo.nix
artiq package should not depend on rustc
I am trying a few things but Rust/cargo are not showing up in nix-store -q -R
in the first place, only in Hydra's Build Dependencies tab.
1cd4056370
libboard_zynq: remove unused eth phy name information
ddff295ae1
libboard_zynq: implement eth hot-plugging
178ab38e35
experiments: delint
3172aba1a8
libboard_zynq: improve i2c doc
a62ca507d0
libregister: allow rustdoc for register! macro
975202a653
libboard_zynq: enable i2c+eeprom for target_kasli_soc
d76a77b443
libregister: s/libregister::/$crate::/
500472b2a8
add feature target_kasli_soc to libsupport_zynq, libconfig, experiments, szl, default.nix
02217f27d1
libcortex_a9: remove useless target_* features
a3eabf1947
libboard_zynq: prepare target_kasli_soc
a32d7abb9a
libboard_zynq: rename ddr DCI_FREQ to DCI_MAX_FREQ
intermittent missing newline in UART output during PLL init
I haven't seen this in a while. Is it always happening to you when the IO PLL is reconfigured, or should we look for something else?
7bbd16f143
default.nix: build crates for all targets
0714162113
rename target_cora_z7_10 to target_coraz7 globally
5b2c779cba
libboard_zynq: delint ps7_init
0a40d4f36d
libboard_zynq: fix zc706 build
55f8d02da8
libboard_zynq: remove ddr-only ps7_init for redpitaya
990fa56d6a
libboard_zynq: complete ddr without ps7_init for redpitaya
8fd317d580
libboard_zynq: remove ps7_init for cora_z7_10
07fedddad9
libboard_zynq: doc ddr size limitation, correct target_redpitaya to 512MB