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intermittent missing newline in UART output during PLL init #49

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opened 2020-07-20 19:49:42 +08:00 by sb10q · 6 comments
sb10q commented 2020-07-20 19:49:42 +08:00
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[     0.028013s] DEBUG(libboard_zynq::clocks::source): Set ARM_PLL to 1600000000 Hz
[     0.009565s] DEBUG(libboard_zynq::clocks::source): Set IO_PLL to 1000000000 Hz[     0.016701s] DEBUG(libboard_zynq::clocks::source): Set DDR_PLL to 1333333332 Hz
[     0.024161s] DEBUG(libboard_zynq::ddr): DDR 3x/2x clocks: 666666660/444444440
[     0.031279s] DEBUG(libboard_zynq::ddr): DDR DCI clock: 10582010 Hz
```text [ 0.028013s] DEBUG(libboard_zynq::clocks::source): Set ARM_PLL to 1600000000 Hz [ 0.009565s] DEBUG(libboard_zynq::clocks::source): Set IO_PLL to 1000000000 Hz[ 0.016701s] DEBUG(libboard_zynq::clocks::source): Set DDR_PLL to 1333333332 Hz [ 0.024161s] DEBUG(libboard_zynq::ddr): DDR 3x/2x clocks: 666666660/444444440 [ 0.031279s] DEBUG(libboard_zynq::ddr): DDR DCI clock: 10582010 Hz ```
astro commented 2020-07-30 00:31:38 +08:00
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Most probable reason:

  • we wait for the UART TX FIFO to be flushed
  • now the last byte ('\n') is in transmission
  • we reset the UART because we just reconfigured the IO PLL
  • the last byte isn't being fully transmitted

Add a delay? Add another dummy byte?

Most probable reason: - we wait for the UART TX FIFO to be flushed - now the last byte ('\n') is in transmission - we reset the UART because we just reconfigured the IO PLL - the last byte isn't being fully transmitted Add a delay? Add another dummy byte?
sb10q commented 2020-07-30 00:58:15 +08:00
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Delay would be ok - I suppose the transmission time is deterministic.

Delay would be ok - I suppose the transmission time is deterministic.
astro was assigned by sb10q 2020-08-13 15:46:22 +08:00
astro commented 2020-08-18 01:40:16 +08:00
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Although I cannot reproduce the problem right now, b268fe015a should fix it for everyone.

Can you confirm?

Although I cannot reproduce the problem right now, b268fe015af2f100aaad470d6c6b4a3ab0f8bb82 should fix it for everyone. Can you confirm?
pca006132 commented 2020-08-25 12:01:59 +08:00
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I still encounter this occasionally.

I still encounter this occasionally.
sb10q commented 2020-09-02 16:54:09 +08:00
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Happened on the NIST board as well.

Happened on the NIST board as well.
astro commented 2020-11-16 23:30:05 +08:00
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I haven't seen this in a while. Is it always happening to you when the IO PLL is reconfigured, or should we look for something else?

I haven't seen this in a while. Is it always happening to you when the IO PLL is reconfigured, or should we look for something else?
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Reference: M-Labs/zynq-rs#49
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