forked from M-Labs/zynq-rs
52 lines
1.0 KiB
Rust
52 lines
1.0 KiB
Rust
#![no_std]
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extern crate alloc;
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/// Re-export so that dependents can always use the same version
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pub use smoltcp;
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pub mod slcr;
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pub mod clocks;
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pub mod uart;
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pub mod devc;
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pub mod stdio;
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pub mod eth;
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pub mod axi_hp;
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pub mod axi_gp;
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pub mod ddr;
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pub mod mpcore;
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pub mod flash;
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pub mod time;
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pub mod timer;
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pub mod sdio;
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pub mod logger;
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pub mod ps7_init;
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pub use libcortex_a9::pl310::L2Cache;
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pub fn l2cache() -> L2Cache {
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const PL310_BASEADDR: usize = 0xF8F02000;
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L2Cache::new(PL310_BASEADDR)
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}
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pub fn setup_l2cache() {
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slcr::RegisterBlock::unlocked(|slcr| {
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assert_eq!(&slcr.unnamed1 as *const _ as u32, 0xF8000A1C);
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unsafe { slcr.unnamed1.write(0x020202); }
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});
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let mut l2 = l2cache();
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use log::info;
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info!("l2 aux={:08X}", l2.regs.aux_control.read());
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// TODO: set prefetch
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// Configure ZYNQ-specific latency
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l2.set_tag_ram_latencies(1, 1, 1);
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l2.set_data_ram_latencies(1, 2, 1);
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l2.disable_interrupts();
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l2.reset_interrupts();
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l2.invalidate_all();
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l2.enable();
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}
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