Astro 4d3b2ac7e5 zynq::ddr: use different data_bus_width for targets ... DDR still works only on the zc706, not on the cora z7-10.		2019-11-11 00:06:35 +01:00
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ddr	zynq::ddr: use different data_bus_width for targets	2019-11-11 00:06:35 +01:00
eth	zynq::eth: remove all memory barriers	2019-11-10 23:52:55 +01:00
uart	Revert "zynq: replace unnecessary slcr::unlocked with new"	2019-11-07 00:13:50 +01:00
axi_gp.rs	add zynq::axi_gp	2019-10-19 01:46:43 +02:00
axi_hp.rs	add zynq::axi_hp	2019-10-18 23:46:00 +02:00
clocks.rs	zynq::clocks: unlock slcr in enable_io()	2019-11-07 00:13:50 +01:00
mod.rs	move slcr, clocks, uart, eth into src/zynq/	2019-10-21 22:19:03 +02:00
slcr.rs	zynq::slcr::unlocked: fix comment	2019-11-07 00:13:50 +01:00