forked from M-Labs/zynq-rs
Compare commits
1 Commits
| Author | SHA1 | Date |
|---|---|---|
 Astro
|
4158906122 |
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@ -98,13 +98,13 @@ dependencies = [
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"libboard_zynq 0.0.0",
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"libcortex_a9 0.0.0",
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"libregister 0.0.0",
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"linked_list_allocator 0.8.4 (registry+https://github.com/rust-lang/crates.io-index)",
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"linked_list_allocator 0.8.3 (registry+https://github.com/rust-lang/crates.io-index)",
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"r0 1.0.0 (registry+https://github.com/rust-lang/crates.io-index)",
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]
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[[package]]
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name = "linked_list_allocator"
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version = "0.8.4"
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version = "0.8.3"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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[[package]]
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@ -170,7 +170,7 @@ dependencies = [
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"checksum cfg-if 0.1.10 (registry+https://github.com/rust-lang/crates.io-index)" = "4785bdd1c96b2a846b2bd7cc02e86b6b3dbf14e7e53446c4f54c92a361040822"
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"checksum compiler_builtins 0.1.27 (registry+https://github.com/rust-lang/crates.io-index)" = "38f18416546abfbf8d801c555a0e99524453e7214f9cc9107ad49de3d5948ccc"
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"checksum embedded-hal 0.2.3 (registry+https://github.com/rust-lang/crates.io-index)" = "ee4908a155094da7723c2d60d617b820061e3b4efcc3d9e293d206a5a76c170b"
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"checksum linked_list_allocator 0.8.4 (registry+https://github.com/rust-lang/crates.io-index)" = "e70e46c13c0e8374c26cec5752e3347ca1087d9711de8f45aa513a7700efd73d"
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"checksum linked_list_allocator 0.8.3 (registry+https://github.com/rust-lang/crates.io-index)" = "d6b60501dd4c850950bb43f970d544f6ce04e0ca021da2db2538fbe9d923f19e"
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"checksum log 0.4.8 (registry+https://github.com/rust-lang/crates.io-index)" = "14b6052be84e6b71ab17edffc2eeabf5c2c3ae1fdb464aae35ac50c67a44e1f7"
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"checksum managed 0.7.1 (registry+https://github.com/rust-lang/crates.io-index)" = "fdcec5e97041c7f0f1c5b7d93f12e57293c831c646f4cc7a5db59460c7ea8de6"
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"checksum nb 0.1.2 (registry+https://github.com/rust-lang/crates.io-index)" = "b1411551beb3c11dedfb0a90a0fa256b47d28b9ec2cdff34c25a2fa59e45dbdc"
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17
README.md
17
README.md
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@ -1,7 +1,7 @@
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# Build
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```shell
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nix-shell --command "cargo xbuild --release -p experiments"
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nix-shell --command "cargo xbuild --release"
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```
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Currently the ELF output is placed at `target/armv7-none-eabihf/release/experiments`
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@ -41,7 +41,7 @@ Proceed using gdb with `load`, `c`
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### Running on the ZC706
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```shell
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nix-shell --command "cargo xbuild --release -p experiments"
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nix-shell --command "cargo xbuild --release"
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cd openocd
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openocd -f zc706.cfg
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```
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@ -57,26 +57,23 @@ openocd -f cora-z7-10.cfg
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### Loading a bitstream into volatile memory
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```shell
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openocd -f zc706.cfg -c "pld load 0 blinker_migen.bit; exit"
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openocd -f zc706.cfg -c "pld load 0 blinker_migen.bit; exit"
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```
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### Development Process
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Clone this repo onto your development/build machine and the raspberry pi that controls the Xilinx 7000 board
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On the dev machine, the below script builds zc706 and secure copies it to the target pi (in your pi $HOME directory):
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On the dev machine, the below script builds zc706 and secure copies it to the target pi (in your pi $HOME directory)
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```shell
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cd ~/zynq-rs
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./build.sh $your_user_or_ssh_id
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cd ~/zc706
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./build.sh $your_user/ssh_id
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```
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On the pi, we need an information rich environment that includes a relatively reliable `gdb` experience (that includes `ctrl-p` and `ctrl-n` command history that persists across `cgdb` executions), run:
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```shell
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ssh pi4
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cd zynq-rs
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# For ZC706, run:
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./tmux.sh 0
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# For Cora Z7, run:
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cd zc706
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./tmux.sh
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```
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2
build.sh
2
build.sh
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@ -1 +1 @@
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nix-shell --command "cargo xbuild --release -p experiments" && scp -C target/armv7-none-eabihf/release/experiments $1@rpi-4.m-labs.hk:/home/$1/zc706/zc706.elf
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nix-shell --command "cargo xbuild --release" && scp -P 2204 -C target/armv7-none-eabihf/release/zc706-experiments $1@nixbld.m-labs.hk:/home/$1/zc706/zc706.elf
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@ -49,7 +49,7 @@ let
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name = "${crate}";
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src = ./.;
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crateSubdir = crate;
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cargoSha256 = "1c1qpg9by8bg93yhgllb5xs155g27qmh99pbrb681wazm8k7nwim";
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cargoSha256 = "0xlynsr94dyv0g41qwk5490w3wnzd5g70msaih6mcbgr3v4s2q34";
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cargoFeatures = features;
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doCheck = false;
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dontFixup = true;
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@ -16,5 +16,5 @@ embedded-hal = "0.2"
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libregister = { path = "../libregister" }
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libcortex_a9 = { path = "../libcortex_a9" }
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libboard_zynq = { path = "../libboard_zynq" }
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libsupport_zynq = { path = "../libsupport_zynq", default-features = false, features = ["panic_handler"]}
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libsupport_zynq = { path = "../libsupport_zynq" }
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libasync = { path = "../libasync" }
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@ -32,23 +32,19 @@ SECTIONS
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*(.bss .bss.*);
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. = ALIGN(4);
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__bss_end = .;
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} > OCM3
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} > OCM
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.stack1 (NOLOAD) : ALIGN(8) {
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__stack1_end = .;
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. += 0x200;
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__stack1_start = .;
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} > OCM3
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} > OCM
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.stack0 (NOLOAD) : ALIGN(8) {
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__stack0_end = .;
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. = ORIGIN(OCM3) + LENGTH(OCM3) - 8;
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. = ORIGIN(OCM) + LENGTH(OCM) - 8;
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__stack0_start = .;
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/* unused heap0 to prevent the linker from complaining*/
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__heap0_start = .;
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__heap0_end = .;
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} > OCM3
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} > OCM
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/DISCARD/ :
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{
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@ -1,7 +1,6 @@
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#![no_std]
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#![no_main]
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#![feature(const_in_array_repeat_expressions)]
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#![feature(naked_functions)]
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extern crate alloc;
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@ -15,9 +14,8 @@ use libboard_zynq::{
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self as zynq,
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clocks::source::{ArmPll, ClockSource, IoPll},
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clocks::Clocks,
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print, println, stdio,
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mpcore,
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gic,
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print, println,
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sdio::sd_card::SdCard,
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smoltcp::{
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iface::{EthernetInterfaceBuilder, NeighborCache, Routes},
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time::Instant,
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@ -25,70 +23,24 @@ use libboard_zynq::{
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},
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time::Milliseconds,
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};
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#[cfg(feature = "target_zc706")]
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use libboard_zynq::ps7_init;
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use libcortex_a9::{
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mutex::Mutex,
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sync_channel::{Sender, Receiver},
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sync_channel,
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regs::{MPIDR, SP},
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spin_lock_yield, notify_spin_lock,
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asm
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};
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use libregister::{RegisterR, RegisterW};
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use libregister::RegisterR;
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use libsupport_zynq::{
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boot, ram,
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};
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use log::{info, warn};
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use core::sync::atomic::{AtomicBool, Ordering};
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const HWADDR: [u8; 6] = [0, 0x23, 0xde, 0xea, 0xbe, 0xef];
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static mut CORE1_REQ: (Sender<usize>, Receiver<usize>) = sync_channel!(usize, 10);
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static mut CORE1_RES: (Sender<usize>, Receiver<usize>) = sync_channel!(usize, 10);
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extern "C" {
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static mut __stack1_start: u32;
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}
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static CORE1_RESTART: AtomicBool = AtomicBool::new(false);
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#[link_section = ".text.boot"]
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#[no_mangle]
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#[naked]
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pub unsafe extern "C" fn IRQ() {
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if MPIDR.read().cpu_id() == 1{
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let mpcore = mpcore::RegisterBlock::new();
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let mut gic = gic::InterruptController::new(mpcore);
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let id = gic.get_interrupt_id();
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if id.0 == 0 {
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gic.end_interrupt(id);
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asm::exit_irq();
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SP.write(&mut __stack1_start as *mut _ as u32);
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asm::enable_irq();
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CORE1_RESTART.store(false, Ordering::Relaxed);
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notify_spin_lock();
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main_core1();
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}
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}
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stdio::drop_uart();
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println!("IRQ");
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loop {}
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}
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pub fn restart_core1() {
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let mut interrupt_controller = gic::InterruptController::new(mpcore::RegisterBlock::new());
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CORE1_RESTART.store(true, Ordering::Relaxed);
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interrupt_controller.send_sgi(gic::InterruptId(0), gic::CPUCore::Core1.into());
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while CORE1_RESTART.load(Ordering::Relaxed) {
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spin_lock_yield();
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}
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}
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#[no_mangle]
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pub fn main_core0() {
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// zynq::clocks::CpuClocks::enable_io(1_250_000_000);
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println!("\nzc706 main");
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let mut interrupt_controller = gic::InterruptController::new(mpcore::RegisterBlock::new());
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interrupt_controller.enable_interrupts();
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// ps7_init::apply();
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libboard_zynq::stdio::drop_uart();
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@ -131,6 +83,26 @@ pub fn main_core0() {
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clocks.cpu_1x()
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);
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// commented out due to OCM full
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// let sd = libboard_zynq::sdio::SDIO::sdio0(true);
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// // only test SD card if it is inserted
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// if sd.is_card_inserted() {
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// let result = SdCard::from_sdio(sd);
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// match &result {
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// Ok(_) => info!("OK!"),
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// Err(a) => info!("{}", a),
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// };
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// const SIZE: usize = 512 * 2 + 1;
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// let mut sd_card = result.unwrap();
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// if false {
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// let buffer: [u8; SIZE] = [5; SIZE];
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// sd_card.write_block(0x0, 2, &buffer).unwrap();
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// }
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// let mut buffer: [u8; SIZE] = [0; SIZE];
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// sd_card.read_block(0 /*0x1*/, 2, &mut buffer[1..]).unwrap();
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// info!("buffer = {:?}", &buffer[..]);
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// }
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let mut flash = zynq::flash::Flash::new(200_000_000).linear_addressing_mode();
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let flash_ram: &[u8] = unsafe { core::slice::from_raw_parts(flash.ptr(), flash.size()) };
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for i in 0..=1 {
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@ -188,68 +160,36 @@ pub fn main_core0() {
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flash = flash_io.stop();
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}
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boot::Core1::start(false);
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if false {
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let core1 = boot::Core1::start(false);
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let core1_req = unsafe { &mut CORE1_REQ.0 };
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let core1_res = unsafe { &mut CORE1_RES.1 };
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let (mut core1_req, rx) = sync_channel!(usize, 10);
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*CORE1_REQ.lock() = Some(rx);
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let (tx, mut core1_res) = sync_channel!(usize, 10);
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*CORE1_RES.lock() = Some(tx);
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task::block_on(async {
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for i in 0..10 {
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restart_core1();
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core1_req.async_send(i).await;
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let j = core1_res.async_recv().await;
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println!("{} -> {}", i, j);
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}
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});
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unsafe {
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core1_req.drop_elements();
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}
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// Test I2C
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#[cfg(feature = "target_zc706")]
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{
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let mut i2c = zynq::i2c::I2C::i2c();
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i2c.init();
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println!("I2C bit-banging enabled");
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let mut eeprom = zynq::i2c::eeprom::EEPROM::new(&mut i2c, 16);
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// Write to 0x00 and 0x08
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let eeprom_buffer: [u8; 22] = [
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0x66, 0x77, 0x88, 0x99, 0xaa, 0xbb,
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0x77, 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee,
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0xef, 0xcd, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01,
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];
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eeprom.write(0x00, &eeprom_buffer[0..6]);
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eeprom.write(0x08, &eeprom_buffer[6..22]);
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println!("Data written to EEPROM");
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let mut eeprom_buffer = [0u8; 24];
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// Read from 0x00
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eeprom.read(0x00, &mut eeprom_buffer);
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print!("Data read from EEPROM @ 0x00: (hex) ");
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for i in 0..6 {
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print!("{:02x} ", eeprom_buffer[i]);
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}
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println!("");
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// Read from 0x08
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eeprom.read(0x08, &mut eeprom_buffer);
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print!("Data read from EEPROM @ 0x08: (hex) ");
|
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for i in 0..16 {
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print!("{:02x} ", eeprom_buffer[i]);
|
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}
|
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println!("");
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core1.disable();
|
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}
|
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|
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let eth = zynq::eth::Eth::default(HWADDR.clone());
|
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println!("Eth on");
|
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|
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const RX_LEN: usize = 4096;
|
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const RX_LEN: usize = 8192;
|
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// Number of transmission buffers (minimum is two because with
|
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// one, duplicate packet transmission occurs)
|
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const TX_LEN: usize = 4096;
|
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const TX_LEN: usize = 8192;
|
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let eth = eth.start_rx(RX_LEN);
|
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let mut eth = eth.start_tx(TX_LEN);
|
||||
|
||||
let ethernet_addr = EthernetAddress(HWADDR);
|
||||
// IP stack
|
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let local_addr = IpAddress::v4(192, 168, 1, 51);
|
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let local_addr = IpAddress::v4(192, 168, 1, 54);
|
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let mut ip_addrs = [IpCidr::new(local_addr, 24)];
|
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let routes = Routes::new(BTreeMap::new());
|
||||
let neighbor_cache = NeighborCache::new(BTreeMap::new());
|
||||
|
|
@ -260,6 +200,9 @@ pub fn main_core0() {
|
|||
.neighbor_cache(neighbor_cache)
|
||||
.finalize();
|
||||
|
||||
#[cfg(feature = "target_zc706")]
|
||||
ps7_init::report_differences();
|
||||
|
||||
Sockets::init(32);
|
||||
|
||||
const TCP_PORT: u16 = 19;
|
||||
|
|
@ -287,7 +230,7 @@ pub fn main_core0() {
|
|||
});
|
||||
let stats_rx = stats.clone();
|
||||
task::spawn(async move {
|
||||
while let Ok(stream) = TcpStream::accept(TCP_PORT+1, 0x10_0000, 0x10_0000).await {
|
||||
while let Ok(stream) = TcpStream::accept(TCP_PORT+1, 4096, 4096).await {
|
||||
let stats_rx = stats_rx.clone();
|
||||
task::spawn(async move {
|
||||
loop {
|
||||
|
|
@ -321,20 +264,38 @@ pub fn main_core0() {
|
|||
}
|
||||
});
|
||||
|
||||
Sockets::run(&mut iface, || {
|
||||
let mut last_stats_time = 0;
|
||||
Sockets::run(&mut iface, |iface| {
|
||||
let t = timer.get_time().0;
|
||||
if t - last_stats_time >= 1000 {
|
||||
let stats = &mut iface.device_mut().stats;
|
||||
info!("eth stats: {:?}", stats);
|
||||
stats.reset();
|
||||
last_stats_time = t;
|
||||
}
|
||||
|
||||
Instant::from_millis(timer.get_time().0 as i64)
|
||||
})
|
||||
}
|
||||
|
||||
static CORE1_REQ: Mutex<Option<sync_channel::Receiver<usize>>> = Mutex::new(None);
|
||||
static CORE1_RES: Mutex<Option<sync_channel::Sender<usize>>> = Mutex::new(None);
|
||||
static DONE: Mutex<bool> = Mutex::new(false);
|
||||
|
||||
#[no_mangle]
|
||||
pub fn main_core1() {
|
||||
println!("Hello from core1!");
|
||||
let mut interrupt_controller = gic::InterruptController::new(mpcore::RegisterBlock::new());
|
||||
interrupt_controller.enable_interrupts();
|
||||
let req = unsafe { &mut CORE1_REQ.1 };
|
||||
let res = unsafe { &mut CORE1_RES.0 };
|
||||
|
||||
let mut req = None;
|
||||
while req.is_none() {
|
||||
req = CORE1_REQ.lock().take();
|
||||
}
|
||||
let req = req.unwrap();
|
||||
let mut res = None;
|
||||
while res.is_none() {
|
||||
res = CORE1_RES.lock().take();
|
||||
}
|
||||
let mut res = res.unwrap();
|
||||
|
||||
for i in req {
|
||||
res.send(i * i);
|
||||
|
|
|
|||
|
|
@ -43,11 +43,11 @@ impl Sockets {
|
|||
/// iface
|
||||
pub fn run<'b, 'c, 'e, D: for<'d> Device<'d>>(
|
||||
iface: &mut EthernetInterface<'b, 'c, 'e, D>,
|
||||
mut get_time: impl FnMut() -> Instant,
|
||||
mut get_time: impl FnMut(&mut EthernetInterface<'b, 'c, 'e, D>) -> Instant,
|
||||
) -> ! {
|
||||
task::block_on(async {
|
||||
loop {
|
||||
let instant = get_time();
|
||||
let instant = get_time(iface);
|
||||
Self::instance().poll(iface, instant);
|
||||
task::r#yield().await;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@ use core::{
|
|||
marker::PhantomData,
|
||||
ops::{Deref, DerefMut},
|
||||
};
|
||||
use log::{debug, info, warn, error};
|
||||
use log::{error, info, warn};
|
||||
use libregister::*;
|
||||
use super::slcr;
|
||||
use super::clocks::Clocks;
|
||||
|
|
@ -132,19 +132,51 @@ fn calculate_tx_divisors(tx_clock: u32) -> (u8, u8) {
|
|||
}
|
||||
}
|
||||
let result = best.unwrap();
|
||||
debug!("Eth TX clock for {}: {} / {} / {} = {}",
|
||||
tx_clock, io_pll,
|
||||
result.0, result.1,
|
||||
io_pll / result.0 as u32 / result.1 as u32
|
||||
info!("Eth TX clock for {}: {} / {} / {} = {}",
|
||||
tx_clock, io_pll,
|
||||
result.0, result.1,
|
||||
io_pll / result.0 as u32 / result.1 as u32
|
||||
);
|
||||
result
|
||||
}
|
||||
|
||||
#[derive(Debug)]
|
||||
pub struct EthStats {
|
||||
frame_recd: usize,
|
||||
no_frame_recd: usize,
|
||||
rx_idle: usize,
|
||||
tx_send: usize,
|
||||
tx_overflow: usize,
|
||||
}
|
||||
|
||||
impl EthStats {
|
||||
pub fn new() -> Self {
|
||||
EthStats {
|
||||
frame_recd: 0,
|
||||
no_frame_recd: 0,
|
||||
rx_idle: 0,
|
||||
tx_send: 0,
|
||||
tx_overflow: 0,
|
||||
}
|
||||
}
|
||||
|
||||
pub fn reset(&mut self) {
|
||||
*self = EthStats {
|
||||
frame_recd: 0,
|
||||
no_frame_recd: 0,
|
||||
rx_idle: 0,
|
||||
tx_send: 0,
|
||||
tx_overflow: 0,
|
||||
};
|
||||
}
|
||||
}
|
||||
|
||||
pub struct Eth<GEM: Gem, RX, TX> {
|
||||
rx: RX,
|
||||
tx: TX,
|
||||
inner: EthInner<GEM>,
|
||||
phy: Phy,
|
||||
pub stats: EthStats,
|
||||
}
|
||||
|
||||
impl Eth<Gem0, (), ()> {
|
||||
|
|
@ -303,6 +335,7 @@ impl<GEM: Gem> Eth<GEM, (), ()> {
|
|||
inner.configure(macaddr);
|
||||
|
||||
let phy = Phy::find(&mut inner).expect("phy");
|
||||
info!("Eth: found PHY {}", phy.name());
|
||||
phy.reset(&mut inner);
|
||||
phy.restart_autoneg(&mut inner);
|
||||
|
||||
|
|
@ -311,6 +344,7 @@ impl<GEM: Gem> Eth<GEM, (), ()> {
|
|||
tx: (),
|
||||
inner,
|
||||
phy,
|
||||
stats: EthStats::new(),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -322,6 +356,7 @@ impl<GEM: Gem, RX, TX> Eth<GEM, RX, TX> {
|
|||
tx: self.tx,
|
||||
inner: self.inner,
|
||||
phy: self.phy,
|
||||
stats: self.stats,
|
||||
};
|
||||
let list_addr = new_self.rx.list_addr();
|
||||
assert!(list_addr & 0b11 == 0);
|
||||
|
|
@ -341,6 +376,7 @@ impl<GEM: Gem, RX, TX> Eth<GEM, RX, TX> {
|
|||
tx: tx::DescList::new(tx_size),
|
||||
inner: self.inner,
|
||||
phy: self.phy,
|
||||
stats: self.stats,
|
||||
};
|
||||
let list_addr = &new_self.tx.list_addr();
|
||||
assert!(list_addr & 0b11 == 0);
|
||||
|
|
@ -387,16 +423,19 @@ impl<GEM: Gem, TX> Eth<GEM, rx::DescList, TX> {
|
|||
let result = self.rx.recv_next();
|
||||
match result {
|
||||
Ok(None) => {
|
||||
self.stats.no_frame_recd += 1;
|
||||
// No packet, clear status bit
|
||||
GEM::regs().rx_status.write(
|
||||
regs::RxStatus::zeroed()
|
||||
.frame_recd(true)
|
||||
);
|
||||
}
|
||||
Ok(Some(_)) => self.stats.frame_recd += 1,
|
||||
_ => {}
|
||||
}
|
||||
result
|
||||
} else {
|
||||
self.stats.rx_idle += 1;
|
||||
self.inner.check_link_change(&self.phy);
|
||||
Ok(None)
|
||||
}
|
||||
|
|
@ -405,7 +444,13 @@ impl<GEM: Gem, TX> Eth<GEM, rx::DescList, TX> {
|
|||
|
||||
impl<GEM: Gem, RX> Eth<GEM, RX, tx::DescList> {
|
||||
pub fn send<'s: 'p, 'p>(&'s mut self, length: usize) -> Option<tx::PktRef<'p>> {
|
||||
self.tx.send(GEM::regs(), length)
|
||||
let result = self.tx.send(GEM::regs(), length);
|
||||
if result.is_some() {
|
||||
self.stats.tx_send += 1;
|
||||
} else {
|
||||
self.stats.tx_overflow += 1;
|
||||
}
|
||||
result
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -432,6 +477,7 @@ impl<'a, GEM: Gem> smoltcp::phy::Device<'a> for &mut Eth<GEM, rx::DescList, tx::
|
|||
fn receive(&'a mut self) -> Option<(Self::RxToken, Self::TxToken)> {
|
||||
match self.rx.recv_next() {
|
||||
Ok(Some(pktref)) => {
|
||||
self.stats.frame_recd += 1;
|
||||
let tx_token = tx::Token {
|
||||
regs: GEM::regs(),
|
||||
desc_list: &mut self.tx,
|
||||
|
|
@ -439,6 +485,7 @@ impl<'a, GEM: Gem> smoltcp::phy::Device<'a> for &mut Eth<GEM, rx::DescList, tx::
|
|||
Some((pktref, tx_token))
|
||||
}
|
||||
Ok(None) => {
|
||||
self.stats.rx_idle += 1;
|
||||
self.inner.check_link_change(&self.phy);
|
||||
None
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,150 +0,0 @@
|
|||
//! ARM Generic Interrupt Controller
|
||||
|
||||
use bit_field::BitField;
|
||||
use libregister::{RegisterW, RegisterRW, RegisterR};
|
||||
use super::mpcore;
|
||||
|
||||
#[derive(Debug, Clone, Copy)]
|
||||
pub struct InterruptId(pub u8);
|
||||
|
||||
#[derive(Debug, Clone, Copy)]
|
||||
#[repr(u8)]
|
||||
pub enum CPUCore {
|
||||
Core0 = 0b01,
|
||||
Core1 = 0b10
|
||||
}
|
||||
|
||||
#[derive(Debug, Clone, Copy)]
|
||||
pub struct TargetCPU(u8);
|
||||
|
||||
impl TargetCPU {
|
||||
pub const fn none() -> TargetCPU {
|
||||
TargetCPU(0)
|
||||
}
|
||||
|
||||
pub const fn and(self, other: TargetCPU) -> TargetCPU {
|
||||
TargetCPU(self.0 | other.0)
|
||||
}
|
||||
}
|
||||
|
||||
impl From<CPUCore> for TargetCPU {
|
||||
fn from(core: CPUCore) -> Self {
|
||||
TargetCPU(core as u8)
|
||||
}
|
||||
}
|
||||
|
||||
pub enum TargetList {
|
||||
CPUList(TargetCPU),
|
||||
Others,
|
||||
This
|
||||
}
|
||||
|
||||
impl From<CPUCore> for TargetList {
|
||||
fn from(core: CPUCore) -> Self {
|
||||
TargetList::CPUList(TargetCPU(core as u8))
|
||||
}
|
||||
}
|
||||
|
||||
impl From<TargetCPU> for TargetList {
|
||||
fn from(cpu: TargetCPU) -> Self {
|
||||
TargetList::CPUList(cpu)
|
||||
}
|
||||
}
|
||||
|
||||
#[derive(Debug, Clone, Copy)]
|
||||
pub enum InterruptSensitivity {
|
||||
Level,
|
||||
Edge,
|
||||
}
|
||||
|
||||
pub struct InterruptController {
|
||||
mpcore: &'static mut mpcore::RegisterBlock,
|
||||
}
|
||||
|
||||
impl InterruptController {
|
||||
pub fn new(mpcore: &'static mut mpcore::RegisterBlock) -> Self {
|
||||
InterruptController { mpcore }
|
||||
}
|
||||
|
||||
pub fn disable_interrupts(&mut self) {
|
||||
self.mpcore.iccicr.modify(|_, w| w.enable_ns(false)
|
||||
.enable_s(false));
|
||||
// FIXME: Should we disable the distributor globally when we disable interrupt (for a single
|
||||
// core)?
|
||||
// self.mpcore.icddcr.modify(|_, w| w.enable_secure(false)
|
||||
// .enable_non_secure(false));
|
||||
}
|
||||
|
||||
/// enable interrupt signaling
|
||||
pub fn enable_interrupts(&mut self) {
|
||||
self.mpcore.iccicr.modify(|_, w| w.enable_ns(true)
|
||||
.enable_s(true));
|
||||
self.mpcore.icddcr.modify(|_, w| w.enable_secure(true));
|
||||
|
||||
// Enable all interrupts except those of the lowest priority.
|
||||
self.mpcore.iccpmr.write(mpcore::ICCPMR::zeroed().priority(0xFF));
|
||||
}
|
||||
|
||||
/// send software generated interrupt
|
||||
pub fn send_sgi(&mut self, id: InterruptId, targets: TargetList) {
|
||||
assert!(id.0 < 16);
|
||||
self.mpcore.icdsgir.modify(|_, w| match targets {
|
||||
TargetList::CPUList(list) => w.target_list_filter(0).cpu_target_list(list.0),
|
||||
TargetList::Others => w.target_list_filter(0b01),
|
||||
TargetList::This => w.target_list_filter(0b10)
|
||||
}.sgiintid(id.0).satt(false));
|
||||
}
|
||||
|
||||
/// enable the interrupt *for this core*.
|
||||
/// Not needed for SGI.
|
||||
pub fn enable(&mut self, id: InterruptId, target_cpu: CPUCore, sensitivity: InterruptSensitivity, priority: u8) {
|
||||
// only 5 bits of the priority is useful
|
||||
assert!(priority < 32);
|
||||
|
||||
self.disable_interrupts();
|
||||
|
||||
// enable
|
||||
let m = (id.0 >> 5) as usize;
|
||||
let n = (id.0 & 0x1F) as usize;
|
||||
assert!(m < 3);
|
||||
unsafe {
|
||||
self.mpcore.icdiser[m].modify(|mut icdiser| *icdiser.set_bit(n, true));
|
||||
}
|
||||
|
||||
// target cpu
|
||||
let m = (id.0 >> 2) as usize;
|
||||
let n = (8 * (id.0 & 3)) as usize;
|
||||
unsafe {
|
||||
self.mpcore.icdiptr[m].modify(|mut icdiptr| *icdiptr.set_bits(n..=n+1, target_cpu as u32 + 1));
|
||||
}
|
||||
|
||||
// sensitivity
|
||||
let m = (id.0 >> 4) as usize;
|
||||
let n = (2 * (id.0 & 0xF)) as usize;
|
||||
unsafe {
|
||||
self.mpcore.icdicfr[m].modify(|mut icdicfr| *icdicfr.set_bits(n..=n+1, match sensitivity {
|
||||
InterruptSensitivity::Level => 0b00,
|
||||
InterruptSensitivity::Edge => 0b10,
|
||||
}));
|
||||
}
|
||||
|
||||
// priority
|
||||
let offset = (id.0 % 4) * 8;
|
||||
let priority: u32 = (priority as u32) << (offset + 3);
|
||||
let mask: u32 = 0xFFFFFFFF ^ (0xFF << offset);
|
||||
unsafe {
|
||||
self.mpcore.icdipr[id.0 as usize / 4].modify(|v| (v & mask) | priority);
|
||||
}
|
||||
|
||||
self.enable_interrupts();
|
||||
}
|
||||
|
||||
pub fn end_interrupt(&mut self, id: InterruptId) {
|
||||
self.mpcore.icceoir.modify(|_, w| w.eoiintid(id.0 as u32));
|
||||
}
|
||||
|
||||
pub fn get_interrupt_id(&self) -> InterruptId {
|
||||
InterruptId(self.mpcore.icciar.read().ackintid() as u8)
|
||||
}
|
||||
|
||||
}
|
||||
|
|
@ -1,107 +0,0 @@
|
|||
use super::I2C;
|
||||
use crate::time::Milliseconds;
|
||||
use embedded_hal::timer::CountDown;
|
||||
|
||||
pub struct EEPROM<'a> {
|
||||
i2c: &'a mut I2C,
|
||||
port: u8,
|
||||
address: u8,
|
||||
page_size: u8,
|
||||
count_down: crate::timer::global::CountDown<Milliseconds>
|
||||
}
|
||||
|
||||
impl<'a> EEPROM<'a> {
|
||||
#[cfg(feature = "target_zc706")]
|
||||
pub fn new(i2c: &'a mut I2C, page_size: u8) -> Self {
|
||||
EEPROM {
|
||||
i2c: i2c,
|
||||
port: 2,
|
||||
address: 0b1010100,
|
||||
page_size: page_size,
|
||||
count_down: unsafe { crate::timer::GlobalTimer::get() }.countdown()
|
||||
}
|
||||
}
|
||||
|
||||
#[cfg(feature = "target_zc706")]
|
||||
fn select(&mut self) -> Result<(), &'static str> {
|
||||
let mask: u16 = 1 << self.port;
|
||||
self.i2c.pca9548_select(0b1110100, mask as u8)?;
|
||||
Ok(())
|
||||
}
|
||||
|
||||
/// Random read
|
||||
pub fn read<'r>(&mut self, addr: u8, buf: &'r mut [u8]) -> Result<(), &'static str> {
|
||||
self.select()?;
|
||||
|
||||
self.i2c.start()?;
|
||||
self.i2c.write(self.address << 1)?;
|
||||
self.i2c.write(addr)?;
|
||||
|
||||
self.i2c.restart()?;
|
||||
self.i2c.write((self.address << 1) | 1)?;
|
||||
let buf_len = buf.len();
|
||||
for (i, byte) in buf.iter_mut().enumerate() {
|
||||
*byte = self.i2c.read(i < buf_len - 1)?;
|
||||
}
|
||||
|
||||
self.i2c.stop()?;
|
||||
|
||||
Ok(())
|
||||
}
|
||||
|
||||
/// Smart multi-page writing
|
||||
/// Using the "Page Write" function of an EEPROM, the memory region for each transaction
|
||||
/// (i.e. from byte `addr` to byte `addr+buf.len()`) should fit under each page
|
||||
/// (i.e. `addr+buf.len()` < `addr/self.page_size+1`); otherwise, a roll-oever occurs,
|
||||
/// where bytes beyond the page end. This smart function takes care of the scenario to avoid
|
||||
/// any roll-over when writing ambiguous memory regions.
|
||||
pub fn write(&mut self, addr: u8, buf: &[u8]) -> Result<(), &'static str> {
|
||||
self.select()?;
|
||||
|
||||
let buf_len = buf.len();
|
||||
let mut pb: u8 = addr % self.page_size;
|
||||
for (i, byte) in buf.iter().enumerate() {
|
||||
if (i == 0) || (pb == 0) {
|
||||
self.i2c.start()?;
|
||||
self.i2c.write(self.address << 1)?;
|
||||
self.i2c.write(addr + (i as u8))?;
|
||||
}
|
||||
self.i2c.write(*byte)?;
|
||||
pb += 1;
|
||||
|
||||
if (i == buf_len-1) || (pb == self.page_size) {
|
||||
self.i2c.stop()?;
|
||||
self.poll(1_000)?;
|
||||
pb = 0;
|
||||
}
|
||||
}
|
||||
|
||||
Ok(())
|
||||
}
|
||||
|
||||
/// Poll
|
||||
pub fn poll(&mut self, timeout_ms: u64) -> Result<(), &'static str> {
|
||||
self.select()?;
|
||||
|
||||
self.count_down.start(Milliseconds(timeout_ms));
|
||||
loop {
|
||||
self.i2c.start()?;
|
||||
let ack = self.i2c.write(self.address << 1)?;
|
||||
self.i2c.stop()?;
|
||||
if ack {
|
||||
break
|
||||
};
|
||||
if !self.count_down.waiting() {
|
||||
return Err("I2C polling timeout")
|
||||
}
|
||||
}
|
||||
|
||||
Ok(())
|
||||
}
|
||||
|
||||
pub fn read_eui48<'r>(&mut self) -> Result<[u8; 6], &'static str> {
|
||||
let mut buffer = [0u8; 6];
|
||||
self.read(0xFA, &mut buffer)?;
|
||||
Ok(buffer)
|
||||
}
|
||||
}
|
||||
|
|
@ -1,235 +0,0 @@
|
|||
//! I2C Bit-banging Controller
|
||||
|
||||
mod regs;
|
||||
pub mod eeprom;
|
||||
use super::clocks::Clocks;
|
||||
use super::slcr;
|
||||
use super::time::Microseconds;
|
||||
use embedded_hal::timer::CountDown;
|
||||
use libregister::{RegisterR, RegisterRW, RegisterW};
|
||||
|
||||
const INVALID_BUS: &'static str = "Invalid I2C bus";
|
||||
|
||||
pub struct I2C {
|
||||
regs: regs::RegisterWrapper,
|
||||
count_down: super::timer::global::CountDown<Microseconds>
|
||||
}
|
||||
|
||||
impl I2C {
|
||||
#[cfg(feature = "target_zc706")]
|
||||
pub fn i2c() -> Self {
|
||||
// Route I2C 0 SCL / SDA Signals to MIO Pins 50 / 51
|
||||
slcr::RegisterBlock::unlocked(|slcr| {
|
||||
// SCL
|
||||
slcr.mio_pin_50.write(
|
||||
slcr::MioPin50::zeroed()
|
||||
.l3_sel(0b000) // as GPIO 50
|
||||
.io_type(slcr::IoBufferType::Lvcmos18)
|
||||
.pullup(true)
|
||||
.disable_rcvr(true)
|
||||
);
|
||||
// SDA
|
||||
slcr.mio_pin_51.write(
|
||||
slcr::MioPin51::zeroed()
|
||||
.l3_sel(0b000) // as GPIO 51
|
||||
.io_type(slcr::IoBufferType::Lvcmos18)
|
||||
.pullup(true)
|
||||
.disable_rcvr(true)
|
||||
);
|
||||
// Reset
|
||||
slcr.gpio_rst_ctrl.reset_gpio();
|
||||
});
|
||||
|
||||
Self::ctor_common(0xFFFF - 0x000C)
|
||||
}
|
||||
|
||||
fn ctor_common(gpio_output_mask: u16) -> Self {
|
||||
// Setup register block
|
||||
let clocks = Clocks::get();
|
||||
let self_ = Self {
|
||||
regs: regs::RegisterWrapper::new(),
|
||||
count_down: unsafe { super::timer::GlobalTimer::get() }.countdown()
|
||||
};
|
||||
|
||||
// Setup GPIO output mask
|
||||
self_.regs.gpio_output_mask.modify(|_, w| {
|
||||
w.mask(gpio_output_mask)
|
||||
});
|
||||
// Setup GPIO driver direction
|
||||
self_.regs.gpio_direction.modify(|_, w| {
|
||||
w.scl(true).sda(true)
|
||||
});
|
||||
|
||||
self_
|
||||
}
|
||||
|
||||
/// Delay for I2C operations, simple wrapper for nb.
|
||||
fn delay_us(&mut self, us: u64) {
|
||||
self.count_down.start(Microseconds(us));
|
||||
nb::block!(self.count_down.wait()).unwrap();
|
||||
}
|
||||
|
||||
fn half_period(&mut self) { self.delay_us(100) }
|
||||
|
||||
fn sda_i(&mut self) -> bool {
|
||||
self.regs.gpio_input.read().sda()
|
||||
}
|
||||
|
||||
fn scl_i(&mut self) -> bool {
|
||||
self.regs.gpio_input.read().scl()
|
||||
}
|
||||
|
||||
fn sda_oe(&mut self, oe: bool) {
|
||||
self.regs.gpio_output_enable.modify(|_, w| {
|
||||
w.sda(oe)
|
||||
})
|
||||
}
|
||||
|
||||
fn sda_o(&mut self, o: bool) {
|
||||
self.regs.gpio_output_mask.modify(|_, w| {
|
||||
w.sda_o(o)
|
||||
})
|
||||
}
|
||||
|
||||
fn scl_oe(&mut self, oe: bool) {
|
||||
self.regs.gpio_output_enable.modify(|_, w| {
|
||||
w.scl(oe)
|
||||
})
|
||||
}
|
||||
|
||||
fn scl_o(&mut self, o: bool) {
|
||||
self.regs.gpio_output_mask.modify(|_, w| {
|
||||
w.scl_o(o)
|
||||
})
|
||||
}
|
||||
|
||||
pub fn init(&mut self) -> Result<(), &'static str> {
|
||||
self.scl_oe(false);
|
||||
self.sda_oe(false);
|
||||
self.scl_o(false);
|
||||
self.sda_o(false);
|
||||
|
||||
// Check the I2C bus is ready
|
||||
self.half_period();
|
||||
self.half_period();
|
||||
if !self.sda_i() {
|
||||
// Try toggling SCL a few times
|
||||
for _bit in 0..8 {
|
||||
self.scl_oe(true);
|
||||
self.half_period();
|
||||
self.scl_oe(false);
|
||||
self.half_period();
|
||||
}
|
||||
}
|
||||
|
||||
if !self.sda_i() {
|
||||
return Err("SDA is stuck low and doesn't get unstuck");
|
||||
}
|
||||
if !self.scl_i() {
|
||||
return Err("SCL is stuck low and doesn't get unstuck");
|
||||
}
|
||||
// postcondition: SCL and SDA high
|
||||
Ok(())
|
||||
}
|
||||
|
||||
pub fn start(&mut self) -> Result<(), &'static str> {
|
||||
// precondition: SCL and SDA high
|
||||
if !self.scl_i() {
|
||||
return Err("SCL is stuck low and doesn't get unstuck");
|
||||
}
|
||||
if !self.sda_i() {
|
||||
return Err("SDA arbitration lost");
|
||||
}
|
||||
self.sda_oe(true);
|
||||
self.half_period();
|
||||
self.scl_oe(true);
|
||||
// postcondition: SCL and SDA low
|
||||
Ok(())
|
||||
}
|
||||
|
||||
pub fn restart(&mut self) -> Result<(), &'static str> {
|
||||
// precondition SCL and SDA low
|
||||
self.sda_oe(false);
|
||||
self.half_period();
|
||||
self.scl_oe(false);
|
||||
self.half_period();
|
||||
self.start()?;
|
||||
// postcondition: SCL and SDA low
|
||||
Ok(())
|
||||
}
|
||||
|
||||
pub fn stop(&mut self) -> Result<(), &'static str> {
|
||||
// precondition: SCL and SDA low
|
||||
self.half_period();
|
||||
self.scl_oe(false);
|
||||
self.half_period();
|
||||
self.sda_oe(false);
|
||||
self.half_period();
|
||||
if !self.sda_i() {
|
||||
return Err("SDA arbitration lost");
|
||||
}
|
||||
// postcondition: SCL and SDA high
|
||||
Ok(())
|
||||
}
|
||||
|
||||
pub fn write(&mut self, data: u8) -> Result<bool, &'static str> {
|
||||
// precondition: SCL and SDA low
|
||||
// MSB first
|
||||
for bit in (0..8).rev() {
|
||||
self.sda_oe(data & (1 << bit) == 0);
|
||||
self.half_period();
|
||||
self.scl_oe(false);
|
||||
self.half_period();
|
||||
self.scl_oe(true);
|
||||
}
|
||||
self.sda_oe(false);
|
||||
self.half_period();
|
||||
self.scl_oe(false);
|
||||
self.half_period();
|
||||
// Read ack/nack
|
||||
let ack = !self.sda_i();
|
||||
self.scl_oe(true);
|
||||
self.sda_oe(true);
|
||||
// postcondition: SCL and SDA low
|
||||
|
||||
Ok(ack)
|
||||
}
|
||||
|
||||
pub fn read(&mut self, ack: bool) -> Result<u8, &'static str> {
|
||||
// precondition: SCL and SDA low
|
||||
self.sda_oe(false);
|
||||
|
||||
let mut data: u8 = 0;
|
||||
|
||||
// MSB first
|
||||
for bit in (0..8).rev() {
|
||||
self.half_period();
|
||||
self.scl_oe(false);
|
||||
self.half_period();
|
||||
if self.sda_i() { data |= 1 << bit }
|
||||
self.scl_oe(true);
|
||||
}
|
||||
// Send ack/nack
|
||||
self.sda_oe(ack);
|
||||
self.half_period();
|
||||
self.scl_oe(false);
|
||||
self.half_period();
|
||||
self.scl_oe(true);
|
||||
self.sda_oe(true);
|
||||
// postcondition: SCL and SDA low
|
||||
|
||||
Ok(data)
|
||||
}
|
||||
|
||||
pub fn pca9548_select(&mut self, address: u8, channels: u8) -> Result<(), &'static str> {
|
||||
self.start()?;
|
||||
if !self.write(address << 1)? {
|
||||
return Err("PCA9548 failed to ack write address")
|
||||
}
|
||||
if !self.write(channels)? {
|
||||
return Err("PCA9548 failed to ack control word")
|
||||
}
|
||||
self.stop()?;
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
|
|
@ -1,93 +0,0 @@
|
|||
use volatile_register::{RO, WO, RW};
|
||||
|
||||
use libregister::{
|
||||
register, register_at,
|
||||
register_bit, register_bits
|
||||
};
|
||||
|
||||
// With reference to:
|
||||
//
|
||||
// artiq:artiq/gateware/targets/kasli.py:
|
||||
// self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
|
||||
//
|
||||
// misoc:misoc/cores/gpio.py:
|
||||
// class GPIOTristate(Module, AutoCSR):
|
||||
// def __init__(self, signals, reset_out=0, reset_oe=0):
|
||||
// l = len(signals)
|
||||
// self._in = CSRStatus(l)
|
||||
// self._out = CSRStorage(l, reset=reset_out)
|
||||
// self._oe = CSRStorage(l, reset=reset_oe)
|
||||
//
|
||||
// Hence, using GPIOs as SCL and SDA GPIOs respectively.
|
||||
//
|
||||
// Current compatibility:
|
||||
// zc706: GPIO 50, 51 == SCL, SDA
|
||||
|
||||
pub struct RegisterWrapper {
|
||||
pub gpio_output_mask: &'static mut GPIOOutputMask,
|
||||
pub gpio_input: &'static mut GPIOInput,
|
||||
pub gpio_direction: &'static mut GPIODirection,
|
||||
pub gpio_output_enable: &'static mut GPIOOutputEnable,
|
||||
}
|
||||
|
||||
impl RegisterWrapper {
|
||||
pub fn new() -> Self {
|
||||
Self {
|
||||
gpio_output_mask: GPIOOutputMask::new(),
|
||||
gpio_input: GPIOInput::new(),
|
||||
gpio_direction: GPIODirection::new(),
|
||||
gpio_output_enable: GPIOOutputEnable::new()
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// MASK_DATA_1_MSW:
|
||||
// Maskable output data for MIO[53:48]
|
||||
register!(gpio_output_mask, GPIOOutputMask, RW, u32);
|
||||
#[cfg(feature = "target_zc706")]
|
||||
register_at!(GPIOOutputMask, 0xE000A00C, new);
|
||||
// Output for SCL
|
||||
#[cfg(feature = "target_zc706")]
|
||||
register_bit!(gpio_output_mask, scl_o, 2);
|
||||
// Output for SDA
|
||||
#[cfg(feature = "target_zc706")]
|
||||
register_bit!(gpio_output_mask, sda_o, 3);
|
||||
// Mask for keeping bits except SCL and SDA unchanged
|
||||
#[cfg(feature = "target_zc706")]
|
||||
register_bits!(gpio_output_mask, mask, u16, 16, 31);
|
||||
|
||||
// DATA_1_RO:
|
||||
// Input data for MIO[53:32]
|
||||
register!(gpio_input, GPIOInput, RO, u32);
|
||||
#[cfg(feature = "target_zc706")]
|
||||
register_at!(GPIOInput, 0xE000A064, new);
|
||||
// Input for SCL
|
||||
#[cfg(feature = "target_zc706")]
|
||||
register_bit!(gpio_input, scl, 18);
|
||||
// Input for SDA
|
||||
#[cfg(feature = "target_zc706")]
|
||||
register_bit!(gpio_input, sda, 19);
|
||||
|
||||
// DIRM_1:
|
||||
// Direction mode for MIO[53:32]; 0/1 = in/out
|
||||
register!(gpio_direction, GPIODirection, RW, u32);
|
||||
#[cfg(feature = "target_zc706")]
|
||||
register_at!(GPIODirection, 0xE000A244, new);
|
||||
// Direction for SCL
|
||||
#[cfg(feature = "target_zc706")]
|
||||
register_bit!(gpio_direction, scl, 18);
|
||||
// Direction for SDA
|
||||
#[cfg(feature = "target_zc706")]
|
||||
register_bit!(gpio_direction, sda, 19);
|
||||
|
||||
// OEN_1:
|
||||
// Output enable for MIO[53:32]
|
||||
register!(gpio_output_enable, GPIOOutputEnable, RW, u32);
|
||||
#[cfg(feature = "target_zc706")]
|
||||
register_at!(GPIOOutputEnable, 0xE000A248, new);
|
||||
// Output enable for SCL
|
||||
#[cfg(feature = "target_zc706")]
|
||||
register_bit!(gpio_output_enable, scl, 18);
|
||||
// Output enable for SDA
|
||||
#[cfg(feature = "target_zc706")]
|
||||
register_bit!(gpio_output_enable, sda, 19);
|
||||
|
|
@ -15,12 +15,9 @@ pub mod axi_hp;
|
|||
pub mod axi_gp;
|
||||
pub mod ddr;
|
||||
pub mod mpcore;
|
||||
pub mod gic;
|
||||
pub mod flash;
|
||||
pub mod time;
|
||||
pub mod timer;
|
||||
pub mod sdio;
|
||||
#[cfg(feature = "target_zc706")]
|
||||
pub mod i2c;
|
||||
pub mod logger;
|
||||
pub mod ps7_init;
|
||||
|
|
|
|||
|
|
@ -8,141 +8,48 @@ use libregister::{
|
|||
|
||||
#[repr(C)]
|
||||
pub struct RegisterBlock {
|
||||
/// SCU Control Register
|
||||
pub scu_control: ScuControl,
|
||||
/// SCU Configuration Register
|
||||
pub scu_config: ScuConfig,
|
||||
/// SCU CPU Power Status Register
|
||||
pub scu_cpu_power_status: SCUCPUPowerStatusRegister,
|
||||
/// SCU Invalidate All Registers in Secure State
|
||||
pub scu_config: RO<u32>,
|
||||
pub scu_cpu_power: RW<u32>,
|
||||
pub scu_invalidate: ScuInvalidate,
|
||||
unused0: [u32; 12],
|
||||
/// Filtering Start Address Register
|
||||
pub filtering_start_address: FilteringStartAddressRegister,
|
||||
/// Defined by FILTEREND input
|
||||
pub filtering_end_address: FilteringEndAddressRegister,
|
||||
unused1: [u32; 2],
|
||||
/// SCU Access Control (SAC) Register
|
||||
pub scu_access_control_sac: SCUAccessControlRegisterSAC,
|
||||
/// SCU Non-secure Access Control Register SNSAC
|
||||
pub scu_non_secure_access_control: SCUNonSecureAccessControlRegister,
|
||||
unused2: [u32; 42],
|
||||
/// CPU Interface Control Register
|
||||
pub iccicr: ICCICR,
|
||||
/// Interrupt Priority Mask Register
|
||||
pub iccpmr: ICCPMR,
|
||||
/// Binary Point Register
|
||||
pub iccbpr: ICCBPR,
|
||||
/// Interrupt Acknowledge Register
|
||||
pub icciar: ICCIAR,
|
||||
/// End Of Interrupt Register
|
||||
pub icceoir: ICCEOIR,
|
||||
/// Running Priority Register
|
||||
pub iccrpr: ICCRPR,
|
||||
/// Highest Pending Interrupt Register
|
||||
pub icchpir: ICCHPIR,
|
||||
/// Aliased Non-secure Binary Point Register
|
||||
pub iccabpr: ICCABPR,
|
||||
unused3: [u32; 55],
|
||||
/// CPU Interface Implementer Identification Register
|
||||
pub iccidr: ICCIDR,
|
||||
/// Global Timer Counter Register 0
|
||||
reserved0: [u32; 12],
|
||||
pub filter_start: RW<u32>,
|
||||
pub filter_end: RW<u32>,
|
||||
reserved1: [u32; 2],
|
||||
pub scu_access_control: RW<u32>,
|
||||
pub scu_non_secure_access_control: RW<u32>,
|
||||
reserved2: [u32; 42],
|
||||
pub iccicr: RW<u32>,
|
||||
pub iccpmw: RW<u32>,
|
||||
pub iccbpr: RW<u32>,
|
||||
pub icciar: RW<u32>,
|
||||
pub icceoir: RW<u32>,
|
||||
pub iccrpr: RW<u32>,
|
||||
pub icchpir: RW<u32>,
|
||||
pub iccabpr: RW<u32>,
|
||||
reserved3: [u32; 55],
|
||||
pub iccidr: RW<u32>,
|
||||
pub global_timer_counter0: ValueRegister,
|
||||
pub global_timer_counter1: ValueRegister,
|
||||
/// Global Timer Control Register
|
||||
pub global_timer_control: GlobalTimerControl,
|
||||
/// Global Timer Interrupt Status Register
|
||||
pub global_timer_interrupt_status: GlobalTimerInterruptStatusRegister,
|
||||
/// Comparator Value Register_0
|
||||
pub global_timer_interrupt_status: RW<u32>,
|
||||
pub comparator_value0: ValueRegister,
|
||||
pub comparator_value1: ValueRegister,
|
||||
/// Auto-increment Register
|
||||
pub auto_increment: RW<u32>,
|
||||
unused4: [u32; 249],
|
||||
/// Private Timer Load Register
|
||||
pub private_timer_load: RW<u32>,
|
||||
/// Private Timer Counter Register
|
||||
pub private_timer_counter: RW<u32>,
|
||||
/// Private Timer Control Register
|
||||
pub private_timer_control: PrivateTimerControlRegister,
|
||||
/// Private Timer Interrupt Status Register
|
||||
pub private_timer_interrupt_status: PrivateTimerInterruptStatusRegister,
|
||||
unused5: [u32; 4],
|
||||
/// Watchdog Load Register
|
||||
pub watchdog_load: RW<u32>,
|
||||
/// Watchdog Counter Register
|
||||
pub watchdog_counter: RW<u32>,
|
||||
/// Watchdog Control Register
|
||||
pub watchdog_control: WatchdogControlRegister,
|
||||
/// Watchdog Interrupt Status Register
|
||||
pub watchdog_interrupt_status: WatchdogInterruptStatusRegister,
|
||||
/// Watchdog Reset Status Register
|
||||
pub watchdog_reset_status: WatchdogResetStatusRegister,
|
||||
/// Watchdog Disable Register
|
||||
pub watchdog_disable: RW<u32>,
|
||||
unused6: [u32; 626],
|
||||
/// Distributor Control Register
|
||||
pub icddcr: ICDDCR,
|
||||
/// Interrupt Controller Type Register
|
||||
pub icdictr: ICDICTR,
|
||||
/// Distributor Implementer Identification Register
|
||||
pub icdiidr: ICDIIDR,
|
||||
unused7: [u32; 29],
|
||||
/// Interrupt Security Register
|
||||
pub icdisr0: RW<u32>,
|
||||
pub icdisr1: RW<u32>,
|
||||
pub icdisr2: RW<u32>,
|
||||
unused8: [u32; 29],
|
||||
/// Interrupt Set-enable Registers
|
||||
pub icdiser: [RW<u32>; 3],
|
||||
unused9: [u32; 29],
|
||||
/// Interrupt Clear-Enable Register 0
|
||||
pub icdicer0: RW<u32>,
|
||||
/// Interrupt Clear-Enable Register 1
|
||||
pub icdicer1: RW<u32>,
|
||||
/// Interrupt Clear-Enable Register 2
|
||||
pub icdicer2: RW<u32>,
|
||||
unused10: [u32; 29],
|
||||
/// Interrupt Set-pending Register
|
||||
pub icdispr0: RW<u32>,
|
||||
pub icdispr1: RW<u32>,
|
||||
pub icdispr2: RW<u32>,
|
||||
unused11: [u32; 29],
|
||||
/// Interrupt Clear-Pending Register
|
||||
pub icdicpr0: RW<u32>,
|
||||
pub icdicpr1: RW<u32>,
|
||||
pub icdicpr2: RW<u32>,
|
||||
unused12: [u32; 29],
|
||||
/// Active Bit register
|
||||
pub icdabr0: RW<u32>,
|
||||
pub icdabr1: RW<u32>,
|
||||
pub icdabr2: RW<u32>,
|
||||
unused13: [u32; 61],
|
||||
/// Interrupt Priority Register
|
||||
pub icdipr: [RW<u32>; 24],
|
||||
unused14: [u32; 232],
|
||||
/// Interrupt Processor Targets Registers
|
||||
pub icdiptr: [RW<u32>; 24],
|
||||
unused15: [u32; 232],
|
||||
/// Interrupt Configuration Registers
|
||||
pub icdicfr: [RW<u32>; 6],
|
||||
unused16: [u32; 58],
|
||||
/// PPI Status Register
|
||||
pub ppi_status: PpiStatus,
|
||||
/// SPI Status Register 0
|
||||
pub spi_status_0: RO<u32>,
|
||||
/// SPI Status Register 1
|
||||
pub spi_status_1: RO<u32>,
|
||||
unused17: [u32; 125],
|
||||
/// Software Generated Interrupt Register
|
||||
pub icdsgir: ICDSGIR,
|
||||
pub auto_increment: ValueRegister,
|
||||
reserved4: [u32; 249],
|
||||
pub private_timer_load: ValueRegister,
|
||||
pub private_timer_counter: ValueRegister,
|
||||
pub private_timer_control: RW<u32>,
|
||||
pub private_timer_interrupt_status: RW<u32>,
|
||||
reserved5: [u32; 4],
|
||||
pub watchdog_load: ValueRegister,
|
||||
pub watchdog_counter: ValueRegister,
|
||||
pub watchdog_control: RW<u32>,
|
||||
pub watchdog_interrupt_status: RW<u32>,
|
||||
// there is plenty more (unimplemented)
|
||||
}
|
||||
|
||||
register_at!(RegisterBlock, 0xF8F00000, new);
|
||||
|
||||
register!(value_register, ValueRegister, RW, u32);
|
||||
register_bits!(value_register, value, u32, 0, 31);
|
||||
|
||||
register!(scu_control, ScuControl, RW, u32);
|
||||
register_bit!(scu_control, ic_standby_enable, 6);
|
||||
register_bit!(scu_control, scu_standby_enable, 5);
|
||||
|
|
@ -158,17 +65,6 @@ impl ScuControl {
|
|||
}
|
||||
}
|
||||
|
||||
register!(scu_config, ScuConfig, RO, u32);
|
||||
register_bits!(scu_config, tag_ram_sizes, u8, 8, 15);
|
||||
register_bits!(scu_config, cpus_smp, u8, 4, 7);
|
||||
register_bits!(scu_config, cpu_number, u8, 0, 1);
|
||||
|
||||
register!(scu_cpu_power_status, SCUCPUPowerStatusRegister, RW, u32);
|
||||
register_bits!(scu_cpu_power_status, cpu3_status, u8, 24, 25);
|
||||
register_bits!(scu_cpu_power_status, cpu2_status, u8, 16, 17);
|
||||
register_bits!(scu_cpu_power_status, cpu1_status, u8, 8, 9);
|
||||
register_bits!(scu_cpu_power_status, cpu0_status, u8, 0, 1);
|
||||
|
||||
register!(scu_invalidate, ScuInvalidate, WO, u32);
|
||||
register_bits!(scu_invalidate, cpu0_ways, u8, 0, 3);
|
||||
register_bits!(scu_invalidate, cpu1_ways, u8, 4, 7);
|
||||
|
|
@ -192,71 +88,8 @@ impl ScuInvalidate {
|
|||
}
|
||||
}
|
||||
|
||||
register!(filtering_start_address, FilteringStartAddressRegister, RW, u32);
|
||||
register_bits!(filtering_start_address, filtering_start_address, u32, 20, 31);
|
||||
register_bits!(filtering_start_address, sbz, u32, 0, 19);
|
||||
|
||||
register!(filtering_end_address, FilteringEndAddressRegister, RW, u32);
|
||||
register_bits!(filtering_end_address, filtering_end_address, u32, 20, 31);
|
||||
register_bits!(filtering_end_address, sbz, u32, 0, 19);
|
||||
|
||||
register!(scu_access_control_sac, SCUAccessControlRegisterSAC, RW, u32);
|
||||
register_bit!(scu_access_control_sac, cp_u3, 3);
|
||||
register_bit!(scu_access_control_sac, cp_u2, 2);
|
||||
register_bit!(scu_access_control_sac, cp_u1, 1);
|
||||
register_bit!(scu_access_control_sac, cp_u0, 0);
|
||||
|
||||
register!(scu_non_secure_access_control, SCUNonSecureAccessControlRegister, RO, u32);
|
||||
register_bits!(scu_non_secure_access_control, sbz, u32, 12, 31);
|
||||
register_bit!(scu_non_secure_access_control, cpu3_global_timer, 11);
|
||||
register_bit!(scu_non_secure_access_control, cpu2_global_timer, 10);
|
||||
register_bit!(scu_non_secure_access_control, cpu1_global_timer, 9);
|
||||
register_bit!(scu_non_secure_access_control, cpu0_global_timer, 8);
|
||||
register_bit!(scu_non_secure_access_control, private_timers_for_cpu3, 7);
|
||||
register_bit!(scu_non_secure_access_control, private_timers_for_cpu2, 6);
|
||||
register_bit!(scu_non_secure_access_control, private_timers_for_cpu1, 5);
|
||||
register_bit!(scu_non_secure_access_control, private_timers_for_cpu0, 4);
|
||||
register_bit!(scu_non_secure_access_control, component_access_for_cpu3, 3);
|
||||
register_bit!(scu_non_secure_access_control, component_access_for_cpu2, 2);
|
||||
register_bit!(scu_non_secure_access_control, component_access_for_cpu1, 1);
|
||||
register_bit!(scu_non_secure_access_control, component_access_for_cpu0, 0);
|
||||
|
||||
register!(iccicr, ICCICR, RW, u32);
|
||||
register_bit!(iccicr, sbpr, 4);
|
||||
register_bit!(iccicr, fiq_en, 3);
|
||||
register_bit!(iccicr, ack_ctl, 2);
|
||||
register_bit!(iccicr, enable_ns, 1);
|
||||
register_bit!(iccicr, enable_s, 0);
|
||||
|
||||
register!(iccpmr, ICCPMR, RW, u32);
|
||||
register_bits!(iccpmr, priority, u8, 0, 7);
|
||||
|
||||
register!(iccbpr, ICCBPR, RW, u32);
|
||||
register_bits!(iccbpr, binary_point, u8, 0, 2);
|
||||
|
||||
register!(icciar, ICCIAR, RW, u32);
|
||||
register_bits!(icciar, cpuid, u8, 10, 12);
|
||||
register_bits!(icciar, ackintid, u32, 0, 9);
|
||||
|
||||
register!(icceoir, ICCEOIR, RW, u32);
|
||||
register_bits!(icceoir, cpuid, u8, 10, 12);
|
||||
register_bits!(icceoir, eoiintid, u32, 0, 9);
|
||||
|
||||
register!(iccrpr, ICCRPR, RW, u32);
|
||||
register_bits!(iccrpr, priority, u8, 0, 7);
|
||||
|
||||
register!(icchpir, ICCHPIR, RW, u32);
|
||||
register_bits!(icchpir, cpuid, u8, 10, 12);
|
||||
register_bits!(icchpir, pendintid, u32, 0, 9);
|
||||
|
||||
register!(iccabpr, ICCABPR, RW, u32);
|
||||
register_bits!(iccabpr, binary_point, u8, 0, 2);
|
||||
|
||||
register!(iccidr, ICCIDR, RO, u32);
|
||||
register_bits!(iccidr, part_number, u32, 20, 31);
|
||||
register_bits!(iccidr, architecture_version, u8, 16, 19);
|
||||
register_bits!(iccidr, revision_number, u8, 12, 15);
|
||||
register_bits!(iccidr, implementer, u32, 0, 11);
|
||||
register!(value_register, ValueRegister, RW, u32);
|
||||
register_bits!(value_register, value, u32, 0, 31);
|
||||
|
||||
register!(global_timer_control, GlobalTimerControl, RW, u32);
|
||||
register_bits!(global_timer_control, prescaler, u8, 8, 15);
|
||||
|
|
@ -264,58 +97,3 @@ register_bit!(global_timer_control, auto_increment_mode, 3);
|
|||
register_bit!(global_timer_control, irq_enable, 2);
|
||||
register_bit!(global_timer_control, comp_enablea, 1);
|
||||
register_bit!(global_timer_control, timer_enable, 0);
|
||||
|
||||
register!(global_timer_interrupt_status, GlobalTimerInterruptStatusRegister, RW, u32);
|
||||
register_bit!(global_timer_interrupt_status, event_flag, 0);
|
||||
|
||||
register!(private_timer_control, PrivateTimerControlRegister, RW, u32);
|
||||
register_bits!(private_timer_control, sbzp, u32, 16, 31);
|
||||
register_bits!(private_timer_control, prescaler, u8, 8, 15);
|
||||
register_bits!(private_timer_control, unk_sbzp, u8, 3, 7);
|
||||
register_bit!(private_timer_control, irq_enable, 2);
|
||||
register_bit!(private_timer_control, auto_reload, 1);
|
||||
register_bit!(private_timer_control, timer_enable, 0);
|
||||
|
||||
register!(private_timer_interrupt_status, PrivateTimerInterruptStatusRegister, RW, u32);
|
||||
register_bits!(private_timer_interrupt_status, unk_sbzp, u32, 1, 31);
|
||||
|
||||
register!(watchdog_control, WatchdogControlRegister, RW, u32);
|
||||
register_bits!(watchdog_control, prescaler, u8, 8, 15);
|
||||
register_bit!(watchdog_control, watchdog_mode, 3);
|
||||
register_bit!(watchdog_control, it_enable, 2);
|
||||
register_bit!(watchdog_control, auto_reload, 1);
|
||||
register_bit!(watchdog_control, watchdog_enable, 0);
|
||||
|
||||
register!(watchdog_interrupt_status, WatchdogInterruptStatusRegister, RW, u32);
|
||||
register_bit!(watchdog_interrupt_status, event_flag, 0);
|
||||
|
||||
register!(watchdog_reset_status, WatchdogResetStatusRegister, RW, u32);
|
||||
register_bit!(watchdog_reset_status, reset_flag, 0);
|
||||
|
||||
register!(icddcr, ICDDCR, RW, u32);
|
||||
register_bit!(icddcr, enable_non_secure, 1);
|
||||
register_bit!(icddcr, enable_secure, 0);
|
||||
|
||||
register!(icdictr, ICDICTR, RO, u32);
|
||||
register_bits!(icdictr, lspi, u8, 11, 15);
|
||||
register_bit!(icdictr, security_extn, 10);
|
||||
register_bits!(icdictr, sbz, u8, 8, 9);
|
||||
register_bits!(icdictr, cpu_number, u8, 5, 7);
|
||||
register_bits!(icdictr, it_lines_number, u8, 0, 4);
|
||||
|
||||
register!(icdiidr, ICDIIDR, RO, u32);
|
||||
register_bits!(icdiidr, implementation_version, u8, 24, 31);
|
||||
register_bits!(icdiidr, revision_number, u32, 12, 23);
|
||||
register_bits!(icdiidr, implementer, u32, 0, 11);
|
||||
|
||||
register!(ppi_status, PpiStatus, RO, u32);
|
||||
register_bits!(ppi_status, ppi_status, u8, 11, 15);
|
||||
register_bits!(ppi_status, sbz, u32, 0, 10);
|
||||
|
||||
register!(icdsgir, ICDSGIR, RW, u32);
|
||||
register_bits!(icdsgir, target_list_filter, u8, 24, 25);
|
||||
register_bits!(icdsgir, cpu_target_list, u8, 16, 23);
|
||||
register_bit!(icdsgir, satt, 15);
|
||||
register_bits!(icdsgir, sbz, u32, 4, 14);
|
||||
register_bits!(icdsgir, sgiintid, u8, 0, 3);
|
||||
|
||||
|
|
|
|||
|
|
@ -132,7 +132,7 @@ pub struct RegisterBlock {
|
|||
pub can_rst_ctrl: RW<u32>,
|
||||
pub i2c_rst_ctrl: RW<u32>,
|
||||
pub uart_rst_ctrl: UartRstCtrl,
|
||||
pub gpio_rst_ctrl: GpioRstCtrl,
|
||||
pub gpio_rst_ctrl: RW<u32>,
|
||||
pub lqspi_rst_ctrl: LqspiRstCtrl,
|
||||
pub smc_rst_ctrl: RW<u32>,
|
||||
pub ocm_rst_ctrl: RW<u32>,
|
||||
|
|
@ -531,20 +531,6 @@ impl UartRstCtrl {
|
|||
}
|
||||
}
|
||||
|
||||
register!(gpio_rst_ctrl, GpioRstCtrl, RW, u32);
|
||||
register_bit!(gpio_rst_ctrl, gpio_cpu1x_rst, 0);
|
||||
register_at!(GpioRstCtrl, 0xF800022C, new);
|
||||
impl GpioRstCtrl {
|
||||
pub fn reset_gpio(&mut self) {
|
||||
self.modify(|_, w|
|
||||
w.gpio_cpu1x_rst(true)
|
||||
);
|
||||
self.modify(|_, w|
|
||||
w.gpio_cpu1x_rst(false)
|
||||
);
|
||||
}
|
||||
}
|
||||
|
||||
register!(lqspi_clk_ctrl, LqspiClkCtrl, RW, u32);
|
||||
register_bit!(lqspi_clk_ctrl, clkact, 0);
|
||||
register_bits_typed!(lqspi_clk_ctrl, src_sel, u8, PllSource, 4, 5);
|
||||
|
|
|
|||
|
|
@ -138,15 +138,6 @@ where
|
|||
}
|
||||
}
|
||||
|
||||
impl<U: PartialOrd> CountDown<U>
|
||||
where
|
||||
GlobalTimer: TimeSource<U>,
|
||||
{
|
||||
pub fn waiting(&self) -> bool {
|
||||
self.timer.now() <= self.timeout
|
||||
}
|
||||
}
|
||||
|
||||
/// embedded-hal sync API
|
||||
impl embedded_hal::blocking::delay::DelayMs<u64> for GlobalTimer {
|
||||
fn delay_ms(&mut self, ms: u64) {
|
||||
|
|
|
|||
|
|
@ -7,7 +7,6 @@ edition = "2018"
|
|||
[features]
|
||||
target_zc706 = []
|
||||
target_cora_z7_10 = []
|
||||
power_saving = []
|
||||
default = ["target_zc706"]
|
||||
|
||||
[dependencies]
|
||||
|
|
|
|||
|
|
@ -33,44 +33,3 @@ pub fn dsb() {
|
|||
pub fn isb() {
|
||||
unsafe { llvm_asm!("isb" :::: "volatile") }
|
||||
}
|
||||
|
||||
/// Enable IRQ
|
||||
#[inline]
|
||||
pub unsafe fn enable_irq() {
|
||||
llvm_asm!("cpsie i":::: "volatile");
|
||||
}
|
||||
|
||||
/// Disable IRQ, return if IRQ was originally enabled.
|
||||
#[inline]
|
||||
pub unsafe fn enter_critical() -> bool {
|
||||
let mut cpsr: u32;
|
||||
llvm_asm!(
|
||||
"mrs $0, cpsr
|
||||
cpsid i"
|
||||
: "=r"(cpsr) ::: "volatile");
|
||||
(cpsr & (1 << 7)) == 0
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub unsafe fn exit_critical(enable: bool) {
|
||||
// https://stackoverflow.com/questions/40019929/temporarily-disable-interrupts-on-arm
|
||||
let mask: u32 = if enable {
|
||||
1 << 7
|
||||
} else {
|
||||
0
|
||||
};
|
||||
llvm_asm!(
|
||||
"mrs r1, cpsr
|
||||
bic r1, r1, $0
|
||||
msr cpsr_c, r1"
|
||||
:: "r"(mask) : "r1");
|
||||
}
|
||||
|
||||
/// Exiting IRQ
|
||||
#[inline]
|
||||
pub unsafe fn exit_irq() {
|
||||
llvm_asm!("
|
||||
mrs r0, SPSR
|
||||
msr CPSR, r0
|
||||
" ::: "r0");
|
||||
}
|
||||
|
|
|
|||
|
|
@ -11,26 +11,9 @@ pub mod cache;
|
|||
pub mod mmu;
|
||||
pub mod mutex;
|
||||
pub mod sync_channel;
|
||||
pub mod semaphore;
|
||||
mod uncached;
|
||||
mod fpu;
|
||||
pub use uncached::UncachedSlice;
|
||||
pub use fpu::enable_fpu;
|
||||
|
||||
global_asm!(include_str!("exceptions.s"));
|
||||
|
||||
#[inline]
|
||||
pub fn spin_lock_yield() {
|
||||
#[cfg(feature = "power_saving")]
|
||||
asm::wfe();
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn notify_spin_lock() {
|
||||
#[cfg(feature = "power_saving")]
|
||||
{
|
||||
asm::dsb();
|
||||
asm::sev();
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -338,7 +338,7 @@ impl L1Table {
|
|||
/* 0xfff00000 - 0xffffffff (256K OCM when mapped to high address space) */
|
||||
self.direct_mapped_section(0xfff, L1Section {
|
||||
global: true,
|
||||
shareable: true,
|
||||
shareable: false,
|
||||
access: AccessPermissions::FullAccess,
|
||||
tex: 0b100,
|
||||
domain: 0,
|
||||
|
|
|
|||
|
|
@ -1,10 +1,20 @@
|
|||
use core::ops::{Deref, DerefMut};
|
||||
use core::sync::atomic::{AtomicU32, Ordering};
|
||||
use core::cell::UnsafeCell;
|
||||
use super::{
|
||||
spin_lock_yield, notify_spin_lock,
|
||||
asm::{dmb, enter_critical, exit_critical}
|
||||
};
|
||||
use super::asm::*;
|
||||
|
||||
/// [Power-saving features](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dht0008a/ch01s03s02.html)
|
||||
#[inline]
|
||||
fn wait_for_update() {
|
||||
wfe();
|
||||
}
|
||||
|
||||
/// [Power-saving features](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dht0008a/ch01s03s02.html)
|
||||
#[inline]
|
||||
fn signal_update() {
|
||||
dsb();
|
||||
sev();
|
||||
}
|
||||
|
||||
const LOCKED: u32 = 1;
|
||||
const UNLOCKED: u32 = 0;
|
||||
|
|
@ -31,26 +41,19 @@ impl<T> Mutex<T> {
|
|||
|
||||
/// Lock the Mutex, blocks when already locked
|
||||
pub fn lock(&self) -> MutexGuard<T> {
|
||||
let mut irq = unsafe { enter_critical() };
|
||||
while self.locked.compare_and_swap(UNLOCKED, LOCKED, Ordering::Acquire) != UNLOCKED {
|
||||
unsafe {
|
||||
exit_critical(irq);
|
||||
spin_lock_yield();
|
||||
irq = enter_critical();
|
||||
}
|
||||
wait_for_update();
|
||||
}
|
||||
dmb();
|
||||
MutexGuard { mutex: self, irq }
|
||||
MutexGuard { mutex: self }
|
||||
}
|
||||
|
||||
pub fn try_lock(&self) -> Option<MutexGuard<T>> {
|
||||
let irq = unsafe { enter_critical() };
|
||||
if self.locked.compare_and_swap(UNLOCKED, LOCKED, Ordering::Acquire) != UNLOCKED {
|
||||
unsafe { exit_critical(irq) };
|
||||
None
|
||||
} else {
|
||||
dmb();
|
||||
Some(MutexGuard { mutex: self, irq })
|
||||
Some(MutexGuard { mutex: self })
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -58,7 +61,7 @@ impl<T> Mutex<T> {
|
|||
dmb();
|
||||
self.locked.store(UNLOCKED, Ordering::Release);
|
||||
|
||||
notify_spin_lock();
|
||||
signal_update();
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -66,7 +69,6 @@ impl<T> Mutex<T> {
|
|||
/// `Deref`/`DerefMutx`
|
||||
pub struct MutexGuard<'a, T> {
|
||||
mutex: &'a Mutex<T>,
|
||||
irq: bool,
|
||||
}
|
||||
|
||||
impl<'a, T> Deref for MutexGuard<'a, T> {
|
||||
|
|
@ -86,6 +88,5 @@ impl<'a, T> DerefMut for MutexGuard<'a, T> {
|
|||
impl<'a, T> Drop for MutexGuard<'a, T> {
|
||||
fn drop(&mut self) {
|
||||
self.mutex.unlock();
|
||||
unsafe { exit_critical(self.irq) };
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,71 +0,0 @@
|
|||
use super::{spin_lock_yield, notify_spin_lock};
|
||||
use core::{
|
||||
task::{Context, Poll},
|
||||
pin::Pin,
|
||||
future::Future,
|
||||
sync::atomic::{AtomicI32, Ordering}
|
||||
};
|
||||
|
||||
pub struct Semaphore {
|
||||
value: AtomicI32,
|
||||
max: i32
|
||||
}
|
||||
|
||||
impl Semaphore {
|
||||
pub fn new(value: i32, max: i32) -> Self {
|
||||
Semaphore { value: AtomicI32::new(value), max}
|
||||
}
|
||||
|
||||
pub fn try_wait(&self) -> Option<()> {
|
||||
loop {
|
||||
let value = self.value.load(Ordering::Relaxed);
|
||||
if value > 0 {
|
||||
if self.value.compare_and_swap(value, value - 1, Ordering::SeqCst) == value {
|
||||
return Some(());
|
||||
}
|
||||
} else {
|
||||
return None;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub fn wait(&self) {
|
||||
while self.try_wait().is_none() {
|
||||
spin_lock_yield();
|
||||
}
|
||||
}
|
||||
|
||||
pub async fn async_wait(&self) {
|
||||
struct Fut<'a>(&'a Semaphore);
|
||||
|
||||
impl Future for Fut<'_> {
|
||||
type Output = ();
|
||||
fn poll(self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Self::Output> {
|
||||
match self.0.try_wait() {
|
||||
Some(_) => Poll::Ready(()),
|
||||
None => {
|
||||
cx.waker().wake_by_ref();
|
||||
Poll::Pending
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Fut(&self).await
|
||||
}
|
||||
|
||||
pub fn signal(&self) {
|
||||
loop {
|
||||
let value = self.value.load(Ordering::Relaxed);
|
||||
if value < self.max {
|
||||
if self.value.compare_and_swap(value, value + 1, Ordering::SeqCst) == value {
|
||||
notify_spin_lock();
|
||||
return;
|
||||
}
|
||||
} else {
|
||||
return;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -6,7 +6,7 @@ use core::{
|
|||
task::{Context, Poll},
|
||||
};
|
||||
use alloc::boxed::Box;
|
||||
use super::{spin_lock_yield, notify_spin_lock};
|
||||
use super::asm::*;
|
||||
|
||||
pub struct Sender<'a, T> where T: Clone {
|
||||
list: &'a [AtomicPtr<T>],
|
||||
|
|
@ -35,7 +35,9 @@ impl<'a, T> Sender<'a, T> where T: Clone {
|
|||
let prev = entry.swap(ptr, Ordering::Relaxed);
|
||||
// we allow other end get it first
|
||||
self.write.store((write + 1) % self.list.len(), Ordering::Release);
|
||||
notify_spin_lock();
|
||||
// wake up other core, actually I wonder if the dsb is really needed...
|
||||
dsb();
|
||||
sev();
|
||||
if !prev.is_null() {
|
||||
unsafe {
|
||||
drop_in_place(prev);
|
||||
|
|
@ -49,7 +51,7 @@ impl<'a, T> Sender<'a, T> where T: Clone {
|
|||
let mut content = content;
|
||||
while let Err(back) = self.try_send(content) {
|
||||
content = back;
|
||||
spin_lock_yield();
|
||||
wfe();
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -85,27 +87,6 @@ impl<'a, T> Sender<'a, T> where T: Clone {
|
|||
content: Err(content.into()),
|
||||
}.await
|
||||
}
|
||||
|
||||
/// free all items in the queue. It is the user's responsibility to
|
||||
/// ensure no reader is trying to copy the data.
|
||||
pub unsafe fn drop_elements(&mut self) {
|
||||
for v in self.list.iter() {
|
||||
let original = v.swap(core::ptr::null_mut(), Ordering::Relaxed);
|
||||
if !original.is_null() {
|
||||
drop_in_place(original);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// Reset the `sync_channel`, *forget* all items in the queue. Affects both the sender and
|
||||
/// receiver.
|
||||
pub unsafe fn reset(&mut self) {
|
||||
self.write.store(0, Ordering::Relaxed);
|
||||
self.read.store(0, Ordering::Relaxed);
|
||||
for v in self.list.iter() {
|
||||
v.store(core::ptr::null_mut(), Ordering::Relaxed);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<'a, T> Receiver<'a, T> where T: Clone {
|
||||
|
|
@ -125,7 +106,9 @@ impl<'a, T> Receiver<'a, T> where T: Clone {
|
|||
};
|
||||
let result = data.clone();
|
||||
self.read.store((read + 1) % self.list.len(), Ordering::Release);
|
||||
notify_spin_lock();
|
||||
// wake up other core, still idk if the dsb is needed...
|
||||
dsb();
|
||||
sev();
|
||||
Ok(result)
|
||||
}
|
||||
}
|
||||
|
|
@ -135,7 +118,7 @@ impl<'a, T> Receiver<'a, T> where T: Clone {
|
|||
if let Ok(data) = self.try_recv() {
|
||||
return data;
|
||||
}
|
||||
spin_lock_yield();
|
||||
wfe();
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -9,10 +9,8 @@ edition = "2018"
|
|||
target_zc706 = ["libboard_zynq/target_zc706"]
|
||||
target_cora_z7_10 = ["libboard_zynq/target_cora_z7_10"]
|
||||
panic_handler = []
|
||||
dummy_irq_handler = []
|
||||
alloc_core = []
|
||||
|
||||
default = ["panic_handler", "dummy_irq_handler"]
|
||||
default = ["panic_handler"]
|
||||
|
||||
[dependencies]
|
||||
r0 = "1"
|
||||
|
|
|
|||
|
|
@ -53,7 +53,6 @@ pub unsafe extern "C" fn ReservedException() {
|
|||
#[link_section = ".text.boot"]
|
||||
#[no_mangle]
|
||||
#[naked]
|
||||
#[cfg(feature = "dummy_irq_handler")]
|
||||
pub unsafe extern "C" fn IRQ() {
|
||||
stdio::drop_uart();
|
||||
println!("IRQ");
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@ use libregister::{
|
|||
VolatileCell,
|
||||
RegisterR, RegisterW, RegisterRW,
|
||||
};
|
||||
use libcortex_a9::{asm, regs::*, cache, mmu, spin_lock_yield, notify_spin_lock};
|
||||
use libcortex_a9::{asm, regs::*, cache, mmu};
|
||||
use libboard_zynq::{slcr, mpcore};
|
||||
|
||||
extern "C" {
|
||||
|
|
@ -29,7 +29,7 @@ pub unsafe extern "C" fn Reset() -> ! {
|
|||
}
|
||||
1 => {
|
||||
while !CORE1_ENABLED.get() {
|
||||
spin_lock_yield();
|
||||
asm::wfe();
|
||||
}
|
||||
SP.write(&mut __stack1_start as *mut _ as u32);
|
||||
boot_core1();
|
||||
|
|
@ -57,7 +57,6 @@ unsafe fn boot_core0() -> ! {
|
|||
asm::dmb();
|
||||
asm::dsb();
|
||||
|
||||
asm::enable_irq();
|
||||
main_core0();
|
||||
panic!("return from main");
|
||||
});
|
||||
|
|
@ -78,7 +77,6 @@ unsafe fn boot_core1() -> ! {
|
|||
asm::dmb();
|
||||
asm::dsb();
|
||||
|
||||
asm::enable_irq();
|
||||
main_core1();
|
||||
panic!("return from main_core1");
|
||||
});
|
||||
|
|
@ -144,7 +142,6 @@ impl Core1 {
|
|||
slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_rst1(false));
|
||||
slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_clkstop1(false));
|
||||
});
|
||||
notify_spin_lock();
|
||||
|
||||
Core1 {}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,97 +1,55 @@
|
|||
use alloc::alloc::Layout;
|
||||
use core::alloc::GlobalAlloc;
|
||||
use core::ptr::NonNull;
|
||||
use libcortex_a9::{
|
||||
mutex::Mutex,
|
||||
regs::MPIDR
|
||||
};
|
||||
use libregister::RegisterR;
|
||||
use alloc::alloc::Layout;
|
||||
use linked_list_allocator::Heap;
|
||||
#[cfg(not(feature = "alloc_core"))]
|
||||
use libcortex_a9::mutex::Mutex;
|
||||
use libboard_zynq::ddr::DdrRam;
|
||||
|
||||
#[global_allocator]
|
||||
static ALLOCATOR: CortexA9Alloc = CortexA9Alloc(
|
||||
Mutex::new(Heap::empty()),
|
||||
Mutex::new(Heap::empty()),
|
||||
);
|
||||
static ALLOCATOR: CortexA9Alloc = CortexA9Alloc(Mutex::new(Heap::empty()));
|
||||
|
||||
struct CortexA9Alloc(Mutex<Heap>, Mutex<Heap>);
|
||||
/// LockedHeap doesn't lock properly
|
||||
struct CortexA9Alloc(Mutex<Heap>);
|
||||
|
||||
unsafe impl Sync for CortexA9Alloc {}
|
||||
|
||||
unsafe impl GlobalAlloc for CortexA9Alloc {
|
||||
unsafe fn alloc(&self, layout: Layout) -> *mut u8 {
|
||||
if cfg!(not(feature = "alloc_core")) || MPIDR.read().cpu_id() == 0 {
|
||||
&self.0
|
||||
} else {
|
||||
&self.1
|
||||
}
|
||||
.lock()
|
||||
.allocate_first_fit(layout)
|
||||
.ok()
|
||||
.map_or(0 as *mut u8, |allocation| allocation.as_ptr())
|
||||
self.0.lock()
|
||||
.allocate_first_fit(layout)
|
||||
.ok()
|
||||
.map_or(0 as *mut u8, |allocation| allocation.as_ptr())
|
||||
}
|
||||
|
||||
unsafe fn dealloc(&self, ptr: *mut u8, layout: Layout) {
|
||||
if cfg!(not(feature = "alloc_core")) || MPIDR.read().cpu_id() == 0 {
|
||||
&self.0
|
||||
} else {
|
||||
&self.1
|
||||
}
|
||||
.lock()
|
||||
.deallocate(NonNull::new_unchecked(ptr), layout)
|
||||
self.0.lock()
|
||||
.deallocate(NonNull::new_unchecked(ptr), layout)
|
||||
}
|
||||
}
|
||||
|
||||
#[cfg(not(feature = "alloc_core"))]
|
||||
pub fn init_alloc_ddr(ddr: &mut DdrRam) {
|
||||
unsafe {
|
||||
ALLOCATOR
|
||||
.0
|
||||
.lock()
|
||||
ALLOCATOR.0.lock()
|
||||
.init(ddr.ptr::<u8>() as usize, ddr.size());
|
||||
}
|
||||
}
|
||||
|
||||
extern "C" {
|
||||
static __heap0_start: usize;
|
||||
static __heap0_end: usize;
|
||||
#[cfg(feature = "alloc_core")]
|
||||
static __heap1_start: usize;
|
||||
#[cfg(feature = "alloc_core")]
|
||||
static __heap1_end: usize;
|
||||
static __heap_start: usize;
|
||||
static __heap_end: usize;
|
||||
}
|
||||
|
||||
pub fn init_alloc_core0() {
|
||||
pub fn init_alloc_linker() {
|
||||
unsafe {
|
||||
let start = &__heap0_start as *const usize as usize;
|
||||
let end = &__heap0_end as *const usize as usize;
|
||||
ALLOCATOR.0.lock().init(start, end - start);
|
||||
let start = &__heap_start as *const usize as usize;
|
||||
let end = &__heap_end as *const usize as usize;
|
||||
ALLOCATOR.0.lock()
|
||||
.init(start, end - start);
|
||||
}
|
||||
}
|
||||
|
||||
#[cfg(feature = "alloc_core")]
|
||||
pub fn init_alloc_core1() {
|
||||
unsafe {
|
||||
let start = &__heap1_start as *const usize as usize;
|
||||
let end = &__heap1_end as *const usize as usize;
|
||||
ALLOCATOR.1.lock().init(start, end - start);
|
||||
}
|
||||
}
|
||||
|
||||
#[alloc_error_handler]
|
||||
fn alloc_error(layout: core::alloc::Layout) -> ! {
|
||||
let id = MPIDR.read().cpu_id();
|
||||
let used = if cfg!(not(feature = "alloc_core")) || id == 0 {
|
||||
ALLOCATOR.0.lock().used()
|
||||
} else {
|
||||
ALLOCATOR.1.lock().used()
|
||||
};
|
||||
panic!(
|
||||
"Core {} alloc_error, layout: {:?}, used memory: {}",
|
||||
id,
|
||||
layout,
|
||||
used
|
||||
);
|
||||
fn alloc_error(_: core::alloc::Layout) -> ! {
|
||||
panic!("alloc_error")
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue