10 Commits (7c8ec46c8fab9927cf889c36f77454b215eca3b0)

Author	SHA1	Message	Date
Astro	7c8ec46c8f	eth: use UncachedSlice for both desc and buffers	2020-07-29 22:25:08 +02:00
Astro	8267acfcba	eth: latter tuning	2020-07-29 22:12:28 +02:00
Astro	7ae8be58cf	eth: fix cache maintenance	2020-07-29 22:12:28 +02:00
Astro	7f3e75e20c	mmu: set L2-bufferable for DDR	2020-07-29 22:12:28 +02:00
Astro	484e385160	eth: implement DeviceCapabilities.max_burst_size ... this is a hint that /could/ boost TCP performance.	2020-07-16 00:17:13 +02:00
Astro	b33ccf83ba	eth: doc	2020-06-18 18:07:50 +02:00
Astro	a80a2c67ef	eth: put desc list behind UncachedSlice, invalidate buffers, add barriers	2020-06-18 01:28:29 +02:00
Astro	a1a211334f	eth: always just allocate desc list + buffers ... buffers are allocated vec anyway. this removes the lifetime hack and further prepares work on cache-line alignment to enable L1 writeback.	2020-06-11 00:21:18 +02:00
Astro	46af38906e	libboard_zynq: wrap eth Buffer for alignment	2020-03-29 00:08:43 +01:00
Astro	cf1983e543	split into lib{register, cortex_a9, board_zynq, board_zc706} crates	2019-12-17 23:35:58 +01:00