18 Commits (1f9ad5ff62e67ddb7f933a5414d541f42b163c6b)

Author	SHA1	Message	Date
Astro	1f9ad5ff62	delint	2019-08-11 00:56:54 +02:00
Astro	b7690c9702	fix UART_REF_CLK ... started to become garbled.	2019-08-07 00:27:01 +02:00
Astro	51c39f032e	run with the cora z7-10	2019-05-25 02:38:48 +02:00
Astro	6bf210366a	regs: properly emit doc_comments	2019-05-24 23:49:49 +02:00
Astro	179c617904	add register_bits_typed! macro	2019-05-23 18:29:05 +02:00
Astro	785e726661	RegisterW/RegisterRW: required &mut self for safety	2019-05-23 18:01:18 +02:00
Astro	62ca26fa71	slcr: abstract with RegisterBlock	2019-05-23 17:52:06 +02:00
Astro	ea62d4fdec	uart: make baudrate configurable, run at 115,200 baud	2019-05-23 15:50:53 +02:00
Astro	7428fec200	uart: add more channel_sts flags, wait for tx_fifo_empty() before sending	2019-05-23 15:36:34 +02:00
Astro	b296fc1d7f	uart: add baud_rate_gen	2019-05-22 01:42:00 +02:00
Astro	43b6d3acd0	uart: wait for reset	2019-05-21 02:53:59 +02:00
Astro	47ec0116a9	use uart1 with more configuration	2019-05-21 01:30:54 +02:00
Astro	7872e00182	uart: move logic outside regs	2019-05-07 17:46:37 +02:00
Astro	275f297309	uart: impl fmt::Write	2019-05-07 16:45:31 +02:00
Astro	ca9b10dce8	refactor regs macros for RO/WO/RW access	2019-05-07 00:32:45 +02:00
Astro	fdc6c38de6	enable_uart0(): add srcsel	2019-05-07 00:01:43 +02:00
Astro	55957eea09	regs macros	2019-05-06 23:56:53 +02:00
Astro	9b414e2408	PoC: boot, uart output in qemu	2019-05-05 14:56:23 +02:00