eth: start_tx

src/eth/mod.rs

@@ -312,6 +312,21 @@ impl<RX, TX> Eth<RX, TX> {
         new_self
     }
 
+    pub fn start_tx<'tx>(self, tx_buffers: [&'tx [u8]; tx::DESCS]) -> Eth<RX, tx::DescList<'tx>> {
+        let new_self = Eth {
+            regs: self.regs,
+            rx: self.rx,
+            tx: tx::DescList::new(tx_buffers),
+        };
+        let list_addr = &new_self.tx as *const _ as u32;
+        assert!(list_addr & 0b11 == 0);
+        new_self.regs.tx_qbar.write(
+            regs::TxQbar::zeroed()
+                .tx_q_baseaddr(list_addr >> 2)
+        );
+        new_self
+    }
+
     fn wait_phy_idle(&self) {
         while !self.regs.net_status.read().phy_mgmt_idle() {}
     }

src/eth/tx.rs

@@ -1,3 +1,4 @@
+use core::mem::uninitialized;
 use crate::{register, register_bit, register_bits, register_bits_typed, regs::*};
 
 /// Descriptor entry
@@ -21,3 +22,32 @@ register_bit!(desc_word1, retry_limit_exceeded, 29);
 register_bit!(desc_word1, wrap, 30);
 /// true if owned by software, false if owned by hardware
 register_bit!(desc_word1, used, 31);
+
+/// Number of descriptors
+pub const DESCS: usize = 8;
+
+#[repr(C)]
+pub struct DescList<'a> {
+    list: [DescEntry; DESCS],
+    buffers: [&'a [u8]; DESCS],
+}
+
+impl<'a> DescList<'a> {
+    pub fn new(buffers: [&'a [u8]; DESCS]) -> Self {
+        let mut list: [DescEntry; DESCS] = unsafe { uninitialized() };
+        for i in 0..DESCS {
+            let buffer_addr = &buffers[i][0] as *const _ as u32;
+            list[i].word0.write(
+                DescWord0::zeroed()
+                    .address(buffer_addr)
+            );
+            list[i].word1.write(
+                DescWord1::zeroed()
+                    .used(true)
+                    .wrap(i == DESCS - 1)
+            );
+        }
+
+        DescList { list, buffers }
+    }
+}