forked from M-Labs/zynq-rs
libboard_zynq: flush Uart by waiting for tx idle
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0f666c570c
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c955eaae7f
@ -29,6 +29,6 @@ impl log::Log for Logger {
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}
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}
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fn flush(&self) {
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fn flush(&self) {
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let uart = stdio::get_uart();
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let uart = stdio::get_uart();
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while !uart.tx_fifo_empty() {}
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while !uart.tx_idle() {}
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}
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}
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}
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}
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@ -63,6 +63,7 @@ macro_rules! println {
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let mut uart = $crate::stdio::get_uart();
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let mut uart = $crate::stdio::get_uart();
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let _ = write!(uart, $($arg)*);
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let _ = write!(uart, $($arg)*);
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let _ = write!(uart, "\n");
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let _ = write!(uart, "\n");
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while !uart.tx_fifo_empty() {}
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// flush after the newline
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while !uart.tx_idle() {}
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})
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})
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}
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}
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@ -221,7 +221,7 @@ impl embedded_hal::serial::Write<u8> for Uart {
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}
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}
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fn flush(&mut self) -> nb::Result<(), Void> {
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fn flush(&mut self) -> nb::Result<(), Void> {
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if self.tx_fifo_empty() {
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if self.tx_idle() {
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Ok(())
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Ok(())
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} else {
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} else {
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Err(nb::Error::WouldBlock)
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Err(nb::Error::WouldBlock)
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