forked from M-Labs/zynq-rs
fix SP init
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parent
b754581452
commit
c88374eab1
15
src/main.rs
15
src/main.rs
@ -29,15 +29,12 @@ pub unsafe extern "C" fn _boot_cores() -> ! {
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use cortex_a9::{asm, regs::*};
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use cortex_a9::{asm, regs::*};
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const CORE_MASK: u32 = 0x3;
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const CORE_MASK: u32 = 0x3;
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// End of OCM RAM
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let stack_start = __end + 4096;
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const STACK_START: u32 = 256 << 10;
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match MPIDR.get() & CORE_MASK {
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match MPIDR.get() & CORE_MASK {
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0 => {
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0 => {
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SP.set(STACK_START);
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SP.set(stack_start);
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zero_bss(&mut __bss_start, &mut __bss_end);
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boot_core0();
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main();
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panic!("return from main");
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}
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}
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_ => loop {
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_ => loop {
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// if not core0, infinitely wait for events
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// if not core0, infinitely wait for events
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@ -46,6 +43,12 @@ pub unsafe extern "C" fn _boot_cores() -> ! {
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}
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}
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}
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}
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unsafe fn boot_core0() -> ! {
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zero_bss(&mut __bss_start, &mut __bss_end);
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main();
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panic!("return from main");
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}
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fn main() {
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fn main() {
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let mut uart = Uart::uart0();
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let mut uart = Uart::uart0();
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writeln!(uart, "Hello World\r").unwrap();
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writeln!(uart, "Hello World\r").unwrap();
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