forked from M-Labs/zynq-rs
libboard_zynq: complete ddr without ps7_init for cora_z7_10
This commit is contained in:
parent
515d3bb381
commit
b9323653bb
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@ -93,8 +93,6 @@ pub fn main_core0() {
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println!("\nZynq experiments");
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let mut interrupt_controller = gic::InterruptController::gic(mpcore::RegisterBlock::mpcore());
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interrupt_controller.enable_interrupts();
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// ps7_init::apply();
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libboard_zynq::stdio::drop_uart();
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libboard_zynq::logger::init().unwrap();
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log::set_max_level(log::LevelFilter::Trace);
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@ -4,7 +4,7 @@ use crate::{print, println};
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use super::slcr::{self, DdriobVrefSel};
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use super::clocks::{Clocks, source::{DdrPll, ClockSource}};
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#[cfg(any(feature = "target_redpitaya", feature = "target_cora_z7_10"))]
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#[cfg(feature = "target_redpitaya")]
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use super::ps7_init;
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mod regs;
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@ -30,18 +30,18 @@ pub struct DdrRam {
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impl DdrRam {
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pub fn ddrram() -> Self {
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if cfg!(any(feature = "target_redpitaya", feature = "target_cora_z7_10")) {
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if cfg!(feature = "target_redpitaya") {
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// We have not yet fixed red pitaya initialization yet. It seems
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// that the clock configuration, iob settings and ddr settings are
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// all problematic
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#[cfg(any(feature = "target_redpitaya", feature = "target_cora_z7_10"))]
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#[cfg(feature = "target_redpitaya")]
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ps7_init::apply();
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let regs = regs::RegisterBlock::ddrc();
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DdrRam { regs }
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} else {
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let clocks = Self::clock_setup();
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Self::calibrate_iob_impedance(&clocks);
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Self::configure_iob();
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Self::calibrate_iob_impedance(&clocks);
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let regs = regs::RegisterBlock::ddrc();
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let mut ddr = DdrRam { regs };
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ddr.reset_ddrc(|ddr| ddr.configure());
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@ -218,12 +218,12 @@ impl DdrRam {
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slcr.ddriob_drive_slew_clock.write(0x00F9861C);
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}
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// Enable external V[REF]
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#[cfg(feature = "target_cora_z7_10")]
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slcr.ddriob_ddr_ctrl.modify(|_, w| w
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.vref_int_en(false)
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.vref_ext_en_lower(true)
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.vref_ext_en_upper(false)
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.refio_en(true)
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);
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#[cfg(feature = "target_zc706")]
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slcr.ddriob_ddr_ctrl.modify(|_, w| w
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@ -242,6 +242,14 @@ impl DdrRam {
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}
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fn configure(&mut self) {
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#[cfg(feature = "target_cora_z7_10")]
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self.regs.dram_param0.write(
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regs::DramParam0::zeroed()
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.t_rc(0x1a)
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.t_rfc_min(0x9e)
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.post_selfref_gap_x32(0x10)
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);
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#[cfg(feature = "target_zc706")]
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self.regs.dram_param0.write(
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regs::DramParam0::zeroed()
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.t_rc(0x1b)
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@ -249,6 +257,17 @@ impl DdrRam {
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.post_selfref_gap_x32(0x10)
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);
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#[cfg(feature = "target_cora_z7_10")]
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self.regs.dram_param1.write(
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regs::DramParam1::zeroed()
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.wr2pre(0x12)
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.powerdown_to_x32(0x6)
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.t_faw(0x15)
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.t_ras_max(0x23)
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.t_ras_min(0x13)
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.t_cke(0x4)
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);
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self.regs.dram_param2.write(
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regs::DramParam2::zeroed()
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.write_latency(0x5)
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@ -260,12 +279,43 @@ impl DdrRam {
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.t_rcd(0x7)
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);
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#[cfg(feature = "target_cora_z7_10")]
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self.regs.dram_param3.write(
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regs::DramParam3::zeroed()
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.t_ccd(4)
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.t_rrd(6)
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.refresh_margin(2)
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.t_rp(7)
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.refresh_to_x32(8)
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.mobile(false)
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.dfi_dram_clk_disable(false)
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.read_latency(7)
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.mode_ddr1_ddr2(true)
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.dis_pad_pd(false)
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);
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self.regs.dram_emr_mr.write(
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regs::DramEmrMr::zeroed()
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.mr(0x930)
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.emr(0x4)
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);
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#[cfg(feature = "target_cora_z7_10")]
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self.regs.dram_burst8_rdwr.write(
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regs::Burst8Rdwr::zeroed()
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.burst_rdwr(4)
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.pre_cke_x1024(0x167)
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.post_cke_x1024(0x1)
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);
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#[cfg(feature = "target_cora_z7_10")]
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self.regs.phy_config2.modify(
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|_, w| w.data_slice_in_use(false)
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);
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#[cfg(feature = "target_cora_z7_10")]
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self.regs.phy_config3.modify(
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|_, w| w.data_slice_in_use(false)
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);
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self.regs.phy_cmd_timeout_rddata_cpt.modify(
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|_, w| w
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.rd_cmd_to_data(0x0)
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@ -298,12 +348,26 @@ impl DdrRam {
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.ctrlup_max(0x40)
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);
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#[cfg(feature = "target_cora_z7_10")]
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self.regs.phy_init_ratio3.write(
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regs::PhyInitRatio::zeroed()
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.wrlvl_init_ratio(0x0)
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.gatelvl_init_ratio(0x76)
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);
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#[cfg(feature = "target_zc706")]
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self.regs.phy_init_ratio3.write(
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regs::PhyInitRatio::zeroed()
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.wrlvl_init_ratio(0x21)
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.gatelvl_init_ratio(0xee)
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);
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#[cfg(feature = "target_cora_z7_10")]
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self.regs.reg_64.modify(
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|_, w| w
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.phy_ctrl_slave_ratio(0x100)
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.phy_invert_clkout(true)
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);
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self.regs.reg_65.write(
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regs::Reg65::zeroed()
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.wr_rl_delay(0x2)
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@ -315,6 +379,18 @@ impl DdrRam {
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.dis_calib_rst(false)
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.ctrl_slave_delay(0x0)
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);
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#[cfg(feature = "target_cora_z7_10")]
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for axi_priority_rd_port in &mut self.regs.axi_priority_rd_ports {
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axi_priority_rd_port.modify(
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|_, w| w
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.arb_pri_rd_portn(0x3ff)
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.arb_disable_aging_rd_portn(false)
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.arb_disable_urgent_rd_portn(false)
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.arb_disable_page_match_rd_portn(false)
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.arb_set_hpr_rd_portn(false)
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);
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}
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}
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/// Reset DDR controller
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@ -370,7 +446,7 @@ impl DdrRam {
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#[cfg(feature = "target_zc706")]
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let megabytes = 1023;
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#[cfg(feature = "target_cora_z7_10")]
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let megabytes = 511;
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let megabytes = 512;
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#[cfg(feature = "target_redpitaya")]
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let megabytes = 511;
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@ -33,14 +33,14 @@ pub struct RegisterBlock {
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pub lpr: RW<u32>,
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pub wr: RW<u32>,
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pub dram_param0: DramParam0,
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pub dram_param1: RW<u32>,
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pub dram_param1: DramParam1,
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pub dram_param2: DramParam2,
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pub dram_param3: RW<u32>,
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pub dram_param3: DramParam3,
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pub dram_param4: RW<u32>,
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pub dram_init_param: RW<u32>,
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pub dram_emr: RW<u32>,
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pub dram_emr_mr: DramEmrMr,
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pub dram_burst8_rdwr: RW<u32>,
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pub dram_burst8_rdwr: Burst8Rdwr,
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pub dram_disable_dq: RW<u32>,
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pub dram_addr_map_bank: RW<u32>,
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pub dram_addr_map_col: RW<u32>,
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@ -84,10 +84,10 @@ pub struct RegisterBlock {
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pub che_ecc_corr_bit_mask_63_32_offset: RW<u32>,
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_unused3: [RO<u32>; 5],
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pub phy_rcvr_enable: RW<u32>,
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pub phy_config0: RW<u32>,
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pub phy_config1: RW<u32>,
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pub phy_config2: RW<u32>,
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pub phy_config3: RW<u32>,
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pub phy_config0: PhyConfig,
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pub phy_config1: PhyConfig,
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pub phy_config2: PhyConfig,
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pub phy_config3: PhyConfig,
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_unused4: RO<u32>,
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pub phy_init_ratio0: PhyInitRatio,
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pub phy_init_ratio1: PhyInitRatio,
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@ -114,7 +114,7 @@ pub struct RegisterBlock {
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pub wr_data_slv2: RW<u32>,
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pub wr_data_slv3: RW<u32>,
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_unused9: RO<u32>,
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pub reg_64: RW<u32>,
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pub reg_64: Reg64,
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pub reg_65: Reg65,
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_unused10: [RO<u32>; 3],
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pub reg69_6a0: RW<u32>,
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@ -142,10 +142,7 @@ pub struct RegisterBlock {
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pub axi_priority_wr_port1: RW<u32>,
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pub axi_priority_wr_port2: RW<u32>,
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pub axi_priority_wr_port3: RW<u32>,
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pub axi_priority_rd_port0: RW<u32>,
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pub axi_priority_rd_port1: RW<u32>,
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pub axi_priority_rd_port2: RW<u32>,
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pub axi_priority_rd_port3: RW<u32>,
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pub axi_priority_rd_ports: [AxiPriorityRd; 4],
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_unused15: [RO<u32>; 27],
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pub excl_access_cfg0: RW<u32>,
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pub excl_access_cfg1: RW<u32>,
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@ -173,6 +170,14 @@ register_bits!(dram_param0, t_rc, u8, 0, 5);
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register_bits!(dram_param0, t_rfc_min, u8, 6, 13);
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register_bits!(dram_param0, post_selfref_gap_x32, u8, 14, 20);
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register!(dram_param1, DramParam1, RW, u32);
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register_bits!(dram_param1, wr2pre, u8, 0, 4);
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register_bits!(dram_param1, powerdown_to_x32, u8, 5, 9);
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register_bits!(dram_param1, t_faw, u8, 10, 15);
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register_bits!(dram_param1, t_ras_max, u8, 16, 21);
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register_bits!(dram_param1, t_ras_min, u8, 22, 26);
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register_bits!(dram_param1, t_cke, u8, 28, 31);
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register!(dram_param2, DramParam2, RW, u32);
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register_bits!(dram_param2, write_latency, u8, 0, 4);
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register_bits!(dram_param2, rd2wr, u8, 5, 9);
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@ -182,10 +187,29 @@ register_bits!(dram_param2, pad_pd, u8, 20, 22);
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register_bits!(dram_param2, rd2pre, u8, 23, 27);
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register_bits!(dram_param2, t_rcd, u8, 28, 31);
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register!(dram_param3, DramParam3, RW, u32);
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register_bits!(dram_param3, t_ccd, u8, 2, 4);
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register_bits!(dram_param3, t_rrd, u8, 5, 7);
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register_bits!(dram_param3, refresh_margin, u8, 8, 11);
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register_bits!(dram_param3, t_rp, u8, 12, 15);
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register_bits!(dram_param3, refresh_to_x32, u8, 16, 20);
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register_bit!(dram_param3, sdram, 21);
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register_bit!(dram_param3, mobile, 22);
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register_bit!(dram_param3, dfi_dram_clk_disable, 23);
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register_bits!(dram_param3, read_latency, u8, 24, 28);
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register_bit!(dram_param3, mode_ddr1_ddr2, 29);
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register_bit!(dram_param3, dis_pad_pd, 30);
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register!(dram_emr_mr, DramEmrMr, RW, u32);
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register_bits!(dram_emr_mr, mr, u16, 0, 15);
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register_bits!(dram_emr_mr, emr, u16, 16, 31);
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register!(burst8_rdwr, Burst8Rdwr, RW, u32);
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register_bits!(burst8_rdwr, burst_rdwr, u8, 0, 3);
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register_bits!(burst8_rdwr, pre_cke_x1024, u16, 4, 13);
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register_bits!(burst8_rdwr, post_cke_x1024, u16, 16, 25);
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register_bit!(burst8_rdwr, burstchop, 28);
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register!(phy_cmd_timeout_rddata_cpt, PhyCmdTimeoutRddataCpt, RW, u32);
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register_bits!(phy_cmd_timeout_rddata_cpt, rd_cmd_to_data, u8, 0, 3);
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register_bits!(phy_cmd_timeout_rddata_cpt, wr_cmd_to_data, u8, 4, 7);
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@ -212,10 +236,27 @@ register_bits!(dfi_timing, rddata_en, u8, 0, 4);
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register_bits!(dfi_timing, ctrlup_min, u16, 5, 14);
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register_bits!(dfi_timing, ctrlup_max, u16, 15, 24);
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register!(phy_config, PhyConfig, RW, u32);
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register_bit!(phy_config, data_slice_in_use, 0);
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register_bit!(phy_config, rdlvl_inc_mode, 1);
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register_bit!(phy_config, gatelvl_inc_mode, 2);
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register_bit!(phy_config, wrlvl_inc_mode, 3);
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register_bits!(phy_config, dq_offset, u8, 24, 30);
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register!(phy_init_ratio, PhyInitRatio, RW, u32);
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register_bits!(phy_init_ratio, wrlvl_init_ratio, u16, 0, 9);
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register_bits!(phy_init_ratio, gatelvl_init_ratio, u16, 10, 19);
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register!(reg_64, Reg64, RW, u32);
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register_bit!(reg_64, phy_bl2, 1);
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register_bit!(reg_64, phy_invert_clkout, 7);
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register_bit!(reg_64, phy_sel_logic, 9);
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register_bits!(reg_64, phy_ctrl_slave_ratio, u16, 10, 19);
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register_bit!(reg_64, phy_ctrl_slave_force, 20);
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register_bits!(reg_64, phy_ctrl_slave_delay, u8, 21, 27);
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register_bit!(reg_64, phy_lpddr, 29);
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register_bit!(reg_64, phy_cmd_latency, 30);
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register!(reg_65, Reg65, RW, u32);
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register_bits!(reg_65, wr_rl_delay, u8, 0, 4);
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register_bits!(reg_65, rd_rl_delay, u8, 5, 9);
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@ -231,3 +272,10 @@ register!(mode_sts_reg,
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ModeStsReg, RO, u32);
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register_bits_typed!(mode_sts_reg, operating_mode, u8, ControllerStatus, 0, 2);
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// (mode_sts_reg) ...
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register!(axi_priority_rd, AxiPriorityRd, RW, u32);
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register_bits!(axi_priority_rd, arb_pri_rd_portn, u16, 0, 9);
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register_bit!(axi_priority_rd, arb_disable_aging_rd_portn, 16);
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register_bit!(axi_priority_rd, arb_disable_urgent_rd_portn, 17);
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register_bit!(axi_priority_rd, arb_disable_page_match_rd_portn, 18);
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register_bit!(axi_priority_rd, arb_set_hpr_rd_portn, 19);
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@ -3978,5 +3978,4 @@ pub const INIT_DATA: &'static [InitOp] = &[
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// .. .. FINISH: NOR CHIP SELECT
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// .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
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// FINISH: top
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];
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