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zynq::clocks: unlock slcr in enable_io()

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Astro 2019-11-06 23:21:22 +01:00
parent 261455877d
commit afd96bd887
1 changed files with 24 additions and 0 deletions
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24
src/zynq/clocks.rs
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@ -90,6 +90,30 @@ impl CpuClocks {
pll / u32::from(uart_clk_ctrl.divisor())
}
/// Zynq-7000 AP SoC Technical Reference Manual:
/// 25.10.4 PLLs
pub fn enable_io(target_clock: u32) {
let fdiv = (target_clock / PS_CLK).min(66) as u16;
slcr::RegisterBlock::unlocked(|slcr| {
slcr.io_pll_ctrl.modify(|_, w| w
.pll_pwrdwn(false)
.pll_bypass_force(true)
.pll_fdiv(fdiv)
);
slcr.io_pll_ctrl.modify(|_, w| w
.pll_reset(true)
);
slcr.io_pll_ctrl.modify(|_, w| w
.pll_reset(false)
);
while ! slcr.pll_status.read().io_pll_lock() {}
slcr.io_pll_ctrl.modify(|_, w| w
.pll_bypass_force(false)
.pll_bypass_qual(false)
);
});
}
/// Zynq-7000 AP SoC Technical Reference Manual:
/// 25.10.4 PLLs
pub fn enable_ddr(target_clock: u32) {