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zynq::flash: enable big endian mode

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Astro 2019-12-10 02:45:05 +01:00
parent f3676c945a
commit aab82f6843
2 changed files with 7 additions and 6 deletions
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12
src/zynq/flash/bytes.rs
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@ -10,7 +10,7 @@ impl<I: Iterator<Item = u32>> BytesTransferExt for I {
fn bytes_transfer(self) -> BytesTransfer<Self> { fn bytes_transfer(self) -> BytesTransfer<Self> {
BytesTransfer { BytesTransfer {
iter: self, iter: self,
shift: 32, shift: 0,
word: 0, word: 0,
} }
} }
@ -26,15 +26,15 @@ impl<I: Iterator<Item = u32> + Sized> Iterator for BytesTransfer<I> {
type Item = u8; type Item = u8;
fn next(&mut self) -> Option<u8> { fn next(&mut self) -> Option<u8> {
if self.shift < 24 { if self.shift > 0 {
self.shift += 8; self.shift -= 8;
Some((self.word >> self.shift) as u8) Some((self.word >> self.shift) as u8)
} else { } else {
self.shift = 0;
self.iter.next() self.iter.next()
.map(|word| { .and_then(|word| {
self.shift = 32;
self.word = word; self.word = word;
word as u8 self.next()
}) })
} }
} }

1
src/zynq/flash/mod.rs
View File

@ -272,6 +272,7 @@ impl Flash<()> {
self.regs.config.modify(|_, w| w self.regs.config.modify(|_, w| w
.man_start_en(true) .man_start_en(true)
.manual_cs(true) .manual_cs(true)
.endian(true)
); );
self.regs.lqspi_cfg.write(regs::LqspiCfg::zeroed() self.regs.lqspi_cfg.write(regs::LqspiCfg::zeroed()