forked from M-Labs/zynq-rs
eth: split into Eth and EthInner
This commit is contained in:
parent
0f6bc68d1f
commit
a76214cb9d
315
src/eth/mod.rs
315
src/eth/mod.rs
@ -17,12 +17,10 @@ const MAX_MDC: u32 = 2_500_000;
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const TX_1000: u32 = 125_000_000;
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pub struct Eth<'r, RX, TX> {
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regs: &'r mut regs::RegisterBlock,
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rx: RX,
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tx: TX,
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link: bool,
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// TODO: no Option
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phy: Option<Phy>,
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inner: EthInner<'r>,
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phy: Phy,
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}
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impl<'r> Eth<'r, (), ()> {
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@ -172,17 +170,21 @@ impl<'r> Eth<'r, (), ()> {
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}
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fn from_regs(regs: &'r mut regs::RegisterBlock, macaddr: [u8; 6]) -> Self {
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let mut eth = Eth {
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let mut inner = EthInner {
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regs,
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link: false,
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};
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inner.init();
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inner.configure(macaddr);
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let phy = Phy::find(&mut inner).expect("phy");
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phy.reset(&mut inner);
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phy.restart_autoneg(&mut inner);
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let mut eth = Eth {
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rx: (),
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tx: (),
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link: false,
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phy: None,
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inner,
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phy,
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};
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eth.init();
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eth.configure(macaddr);
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eth.phy = Phy::find(&mut eth);
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eth.reset_phy();
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eth
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}
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}
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@ -234,6 +236,145 @@ impl<'r, RX, TX> Eth<'r, RX, TX> {
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});
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}
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pub fn start_rx<'rx>(self, rx_list: &'rx mut [rx::DescEntry], rx_buffers: &'rx mut [[u8; MTU]]) -> Eth<'r, rx::DescList<'rx>, TX> {
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let new_self = Eth {
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rx: rx::DescList::new(rx_list, rx_buffers),
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tx: self.tx,
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inner: self.inner,
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phy: self.phy,
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};
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let list_addr = new_self.rx.list_addr();
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assert!(list_addr & 0b11 == 0);
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new_self.inner.regs.rx_qbar.write(
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regs::RxQbar::zeroed()
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.rx_q_baseaddr(list_addr >> 2)
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);
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new_self.inner.regs.net_ctrl.modify(|_, w|
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w.rx_en(true)
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);
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new_self
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}
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pub fn start_tx<'tx>(self, tx_list: &'tx mut [tx::DescEntry], tx_buffers: &'tx mut [[u8; MTU]]) -> Eth<'r, RX, tx::DescList<'tx>> {
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let new_self = Eth {
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rx: self.rx,
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tx: tx::DescList::new(tx_list, tx_buffers),
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inner: self.inner,
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phy: self.phy,
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};
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let list_addr = &new_self.tx.list_addr();
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assert!(list_addr & 0b11 == 0);
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new_self.inner.regs.tx_qbar.write(
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regs::TxQbar::zeroed()
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.tx_q_baseaddr(list_addr >> 2)
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);
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new_self.inner.regs.net_ctrl.modify(|_, w|
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w.tx_en(true)
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);
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new_self
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}
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}
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impl<'r, 'rx, TX> Eth<'r, rx::DescList<'rx>, TX> {
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pub fn recv_next<'s: 'p, 'p>(&'s mut self) -> Result<Option<rx::PktRef<'p>>, rx::Error> {
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let status = self.inner.regs.rx_status.read();
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if status.hresp_not_ok() {
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// Clear
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self.inner.regs.rx_status.write(
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regs::RxStatus::zeroed()
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.hresp_not_ok(true)
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);
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return Err(rx::Error::HrespNotOk);
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}
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if status.rx_overrun() {
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// Clear
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self.inner.regs.rx_status.write(
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regs::RxStatus::zeroed()
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.rx_overrun(true)
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);
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return Err(rx::Error::RxOverrun);
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}
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if status.buffer_not_avail() {
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// Clear
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self.inner.regs.rx_status.write(
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regs::RxStatus::zeroed()
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.buffer_not_avail(true)
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);
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return Err(rx::Error::BufferNotAvail);
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}
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if status.frame_recd() {
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let result = self.rx.recv_next();
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match result {
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Ok(None) => {
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// No packet, clear status bit
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self.inner.regs.rx_status.write(
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regs::RxStatus::zeroed()
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.frame_recd(true)
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);
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}
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_ => {}
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}
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result
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} else {
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self.inner.check_link_change(&self.phy);
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Ok(None)
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}
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}
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}
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impl<'r, 'tx, RX> Eth<'r, RX, tx::DescList<'tx>> {
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pub fn send<'s: 'p, 'p>(&'s mut self, length: usize) -> Option<tx::PktRef<'p>> {
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self.tx.send(self.inner.regs, length)
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}
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}
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impl<'r, 'rx, 'tx: 'a, 'a> smoltcp::phy::Device<'a> for &mut Eth<'r, rx::DescList<'rx>, tx::DescList<'tx>> {
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type RxToken = rx::PktRef<'a>;
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type TxToken = tx::Token<'a, 'tx>;
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fn capabilities(&self) -> smoltcp::phy::DeviceCapabilities {
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let mut caps = smoltcp::phy::DeviceCapabilities::default();
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caps.max_transmission_unit = MTU;
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caps
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}
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fn receive(&'a mut self) -> Option<(Self::RxToken, Self::TxToken)> {
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match self.rx.recv_next() {
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Ok(Some(mut pktref)) => {
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let tx_token = tx::Token {
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regs: self.inner.regs,
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desc_list: &mut self.tx,
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};
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Some((pktref, tx_token))
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}
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Ok(None) => {
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self.inner.check_link_change(&self.phy);
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None
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}
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Err(e) => {
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println!("eth recv error: {:?}", e);
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None
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}
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}
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}
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fn transmit(&'a mut self) -> Option<Self::TxToken> {
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Some(tx::Token {
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regs: self.inner.regs,
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desc_list: &mut self.tx,
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})
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}
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}
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struct EthInner<'r> {
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regs: &'r mut regs::RegisterBlock,
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link: bool,
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}
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impl<'r> EthInner<'r> {
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fn init(&mut self) {
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// Clear the Network Control register.
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self.regs.net_ctrl.write(regs::NetCtrl::zeroed());
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@ -356,74 +497,21 @@ impl<'r, RX, TX> Eth<'r, RX, TX> {
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);
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}
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pub fn start_rx<'rx>(self, rx_list: &'rx mut [rx::DescEntry], rx_buffers: &'rx mut [[u8; MTU]]) -> Eth<'r, rx::DescList<'rx>, TX> {
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let new_self = Eth {
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regs: self.regs,
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rx: rx::DescList::new(rx_list, rx_buffers),
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tx: self.tx,
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link: self.link,
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phy: self.phy,
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};
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let list_addr = new_self.rx.list_addr();
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assert!(list_addr & 0b11 == 0);
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new_self.regs.rx_qbar.write(
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regs::RxQbar::zeroed()
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.rx_q_baseaddr(list_addr >> 2)
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);
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new_self.regs.net_ctrl.modify(|_, w|
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w.rx_en(true)
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);
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new_self
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}
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pub fn start_tx<'tx>(self, tx_list: &'tx mut [tx::DescEntry], tx_buffers: &'tx mut [[u8; MTU]]) -> Eth<'r, RX, tx::DescList<'tx>> {
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let new_self = Eth {
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regs: self.regs,
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rx: self.rx,
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tx: tx::DescList::new(tx_list, tx_buffers),
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link: self.link,
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phy: self.phy,
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};
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let list_addr = &new_self.tx.list_addr();
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assert!(list_addr & 0b11 == 0);
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new_self.regs.tx_qbar.write(
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regs::TxQbar::zeroed()
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.tx_q_baseaddr(list_addr >> 2)
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);
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new_self.regs.net_ctrl.modify(|_, w|
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w.tx_en(true)
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);
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new_self
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}
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fn wait_phy_idle(&self) {
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while !self.regs.net_status.read().phy_mgmt_idle() {}
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}
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pub fn reset_phy(&mut self) {
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let phy = self.phy.clone().expect("phy");
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println!("eth: Reset PHY at {}: {}", phy.addr, phy.name());
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phy.modify_control(self, |control|
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control.set_reset(true)
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);
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while phy.get_control(self).reset() {
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println!("eth: Wait for PHY reset");
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}
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phy.modify_control(self, |control|
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control.set_autoneg_enable(true)
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.set_restart_autoneg(true)
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);
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}
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fn check_link_change(&mut self) {
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let phy = self.phy.clone().expect("phy");
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fn check_link_change(&mut self, phy: &Phy) {
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let link = phy.get_status(self).link_status();
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// Check link state transition
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match (self.link, link) {
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(false, true) => {
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println!("eth: got link, setting clock for gigabit");
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Self::setup_gem0_clock(TX_1000);
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// TODO: should derive gem0/gem107
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Eth::<(), ()>::setup_gem0_clock(TX_1000);
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}
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(true, false) => {
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println!("eth: link lost");
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@ -439,61 +527,7 @@ impl<'r, RX, TX> Eth<'r, RX, TX> {
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}
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}
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impl<'r, 'rx, TX> Eth<'r, rx::DescList<'rx>, TX> {
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pub fn recv_next<'s: 'p, 'p>(&'s mut self) -> Result<Option<rx::PktRef<'p>>, rx::Error> {
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let status = self.regs.rx_status.read();
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if status.hresp_not_ok() {
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// Clear
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self.regs.rx_status.write(
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regs::RxStatus::zeroed()
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.hresp_not_ok(true)
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);
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return Err(rx::Error::HrespNotOk);
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}
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if status.rx_overrun() {
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// Clear
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self.regs.rx_status.write(
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regs::RxStatus::zeroed()
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.rx_overrun(true)
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);
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return Err(rx::Error::RxOverrun);
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}
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if status.buffer_not_avail() {
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// Clear
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self.regs.rx_status.write(
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regs::RxStatus::zeroed()
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.buffer_not_avail(true)
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);
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return Err(rx::Error::BufferNotAvail);
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}
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if status.frame_recd() {
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let result = self.rx.recv_next();
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match result {
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Ok(None) => {
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// No packet, clear status bit
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self.regs.rx_status.write(
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regs::RxStatus::zeroed()
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.frame_recd(true)
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);
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}
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_ => {}
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}
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result
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} else {
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self.check_link_change();
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Ok(None)
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}
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}
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}
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impl<'r, 'tx, RX> Eth<'r, RX, tx::DescList<'tx>> {
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pub fn send<'s: 'p, 'p>(&'s mut self, length: usize) -> Option<tx::PktRef<'p>> {
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self.tx.send(self.regs, length)
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}
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}
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impl<'r, RX, TX> PhyAccess for Eth<'r, RX, TX> {
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impl<'r> PhyAccess for EthInner<'r> {
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fn read_phy(&mut self, addr: u8, reg: u8) -> u16 {
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self.wait_phy_idle();
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self.regs.phy_maint.write(
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@ -523,41 +557,4 @@ impl<'r, RX, TX> PhyAccess for Eth<'r, RX, TX> {
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}
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}
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impl<'r, 'rx, 'tx: 'a, 'a> smoltcp::phy::Device<'a> for &mut Eth<'r, rx::DescList<'rx>, tx::DescList<'tx>> {
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type RxToken = rx::PktRef<'a>;
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type TxToken = tx::Token<'a, 'tx>;
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fn capabilities(&self) -> smoltcp::phy::DeviceCapabilities {
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let mut caps = smoltcp::phy::DeviceCapabilities::default();
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caps.max_transmission_unit = MTU;
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caps
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}
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fn receive(&'a mut self) -> Option<(Self::RxToken, Self::TxToken)> {
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match self.rx.recv_next() {
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Ok(Some(mut pktref)) => {
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let tx_token = tx::Token {
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regs: self.regs,
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desc_list: &mut self.tx,
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};
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Some((pktref, tx_token))
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}
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Ok(None) => {
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// TODO: self.check_link_change();
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None
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}
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Err(e) => {
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println!("eth recv error: {:?}", e);
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None
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}
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}
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}
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fn transmit(&'a mut self) -> Option<Self::TxToken> {
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Some(tx::Token {
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regs: self.regs,
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desc_list: &mut self.tx,
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})
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}
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}
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@ -93,6 +93,20 @@ impl Phy {
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pub fn get_status<PA: PhyAccess>(&self, pa: &mut PA) -> Status {
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self.read_reg(pa)
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}
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pub fn reset<PA: PhyAccess>(&self, pa: &mut PA) {
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self.modify_control(pa, |control|
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control.set_reset(true)
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);
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while self.get_control(pa).reset() {}
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}
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pub fn restart_autoneg<PA: PhyAccess>(&self, pa: &mut PA) {
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self.modify_control(pa, |control|
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control.set_autoneg_enable(true)
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.set_restart_autoneg(true)
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);
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}
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}
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pub trait PhyRegister {
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