forked from M-Labs/zynq-rs
libboard_zynq: rename ddr DCI_FREQ to DCI_MAX_FREQ
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@ -20,8 +20,7 @@ const DDR_FREQ: u32 = 525_000_000;
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/// Alliance Memory AS4C256M16D3B: 800 MHz DDR3 at 533 MHz
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const DDR_FREQ: u32 = 533_333_333;
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/// MT41K256M16HA-125
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const DCI_FREQ: u32 = 10_000_000;
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const DCI_MAX_FREQ: u32 = 10_000_000;
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pub struct DdrRam {
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regs: &'static mut regs::RegisterBlock,
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@ -61,7 +60,7 @@ impl DdrRam {
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}
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fn calculate_dci_divisors(clocks: &Clocks) -> (u8, u8) {
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let target = (DCI_FREQ - 1 + clocks.ddr) / DCI_FREQ;
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let target = (DCI_MAX_FREQ - 1 + clocks.ddr) / DCI_MAX_FREQ;
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let mut best = None;
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let mut best_error = 0;
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