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zynq::ddr: wait for init

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This commit is contained in:
Astro 2019-10-25 19:09:54 +02:00
parent 4cf5283ba8
commit 838434cdec
2 changed files with 37 additions and 8 deletions
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23
src/zynq/ddr/mod.rs
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@ -8,7 +8,9 @@ mod regs;
const DDR_FREQ: u32 = 666_666_666; const DDR_FREQ: u32 = 666_666_666;
const DCI_FREQ: u32 = 10_000_000; const DCI_FREQ: u32 = 10_000_000;
pub struct DdrRam; pub struct DdrRam {
regs: &'static mut regs::RegisterBlock,
}
impl DdrRam { impl DdrRam {
pub fn new() -> Self { pub fn new() -> Self {
@ -16,9 +18,11 @@ impl DdrRam {
Self::clock_setup(&clocks); Self::clock_setup(&clocks);
Self::calibrate_iob_impedance(&clocks); Self::calibrate_iob_impedance(&clocks);
Self::configure_iob(); Self::configure_iob();
Self::reset_ddrc();
DdrRam let regs = unsafe { regs::RegisterBlock::new() };
let mut ddr = DdrRam { regs };
ddr.reset_ddrc();
ddr
} }
/// Zynq-7000 AP SoC Technical Reference Manual: /// Zynq-7000 AP SoC Technical Reference Manual:
@ -133,15 +137,20 @@ impl DdrRam {
} }
/// Reset DDR controller /// Reset DDR controller
fn reset_ddrc() { fn reset_ddrc(&mut self) {
let regs = unsafe { regs::RegisterBlock::new() }; self.regs.ddrc_ctrl.modify(|_, w| w
regs.ddrc_ctrl.modify(|_, w| w
.soft_rstb(false) .soft_rstb(false)
); );
regs.ddrc_ctrl.modify(|_, w| w self.regs.ddrc_ctrl.modify(|_, w| w
.soft_rstb(true) .soft_rstb(true)
.powerdown_en(false) .powerdown_en(false)
.data_bus_width(regs::DataBusWidth::Width32bit) .data_bus_width(regs::DataBusWidth::Width32bit)
); );
while self.status() == regs::ControllerStatus::Init {}
}
pub fn status(&self) -> regs::ControllerStatus {
self.regs.mode_sts_reg.read().operating_mode()
} }
} }

22
src/zynq/ddr/regs.rs
View File

@ -8,6 +8,21 @@ pub enum DataBusWidth {
Width16bit = 0b01, Width16bit = 0b01,
} }
#[derive(Debug, Clone, PartialEq)]
#[repr(u8)]
pub enum ControllerStatus {
Init = 0,
Normal = 1,
Powerdown = 2,
SelfRefresh = 3,
Powerdown1 = 4,
Powerdown2 = 5,
Powerdown3 = 6,
Powerdown4 = 7,
}
#[repr(C)] #[repr(C)]
pub struct RegisterBlock { pub struct RegisterBlock {
pub ddrc_ctrl: DdrcCtrl, pub ddrc_ctrl: DdrcCtrl,
@ -31,7 +46,7 @@ pub struct RegisterBlock {
pub dram_odt_reg: RW<u32>, pub dram_odt_reg: RW<u32>,
pub phy_dbg_reg: RW<u32>, pub phy_dbg_reg: RW<u32>,
pub phy_cmd_timeout_rddata_cpt: RW<u32>, pub phy_cmd_timeout_rddata_cpt: RW<u32>,
pub mode_sts_reg: RW<u32>, pub mode_sts_reg: ModeStsReg,
pub dll_calib: RW<u32>, pub dll_calib: RW<u32>,
pub odt_delay_hold: RW<u32>, pub odt_delay_hold: RW<u32>,
pub ctrl_reg1: RW<u32>, pub ctrl_reg1: RW<u32>,
@ -154,3 +169,8 @@ register_bit!(ddrc_ctrl,
register_bit!(ddrc_ctrl, powerdown_en, 1); register_bit!(ddrc_ctrl, powerdown_en, 1);
register_bits_typed!(ddrc_ctrl, data_bus_width, u8, DataBusWidth, 2, 3); register_bits_typed!(ddrc_ctrl, data_bus_width, u8, DataBusWidth, 2, 3);
// (ddrc_ctrl) ... // (ddrc_ctrl) ...
/// Controller operation mode status
register!(mode_sts_reg, ModeStsReg, RO, u32);
register_bits_typed!(mode_sts_reg, operating_mode, u8, ControllerStatus, 0, 2);
// (mode_sts_reg) ...