mmu: set L2-bufferable for DDR

experiments/src/main.rs

@@ -85,6 +85,7 @@ pub fn main_core0() {
     );
     info!("Setup L2Cache");
     setup_l2cache();
+    info!("L2Cache done");
 
     // commented out due to OCM full
     // let sd = libboard_zynq::sdio::SDIO::sdio0(true);
@@ -124,6 +125,7 @@ pub fn main_core0() {
     ddr.memtest();
     ram::init_alloc_ddr(&mut ddr);
 
+if false {
     #[cfg(dev)]
     for i in 0..=1 {
         let mut flash_io = flash.manual_mode(i);
@@ -177,6 +179,7 @@ pub fn main_core0() {
         }
     });
     core1.disable();
+}
 
     let eth = zynq::eth::Eth::default(HWADDR.clone());
     println!("Eth on");

libboard_zynq/Cargo.toml

@@ -21,5 +21,5 @@ libcortex_a9 = { path = "../libcortex_a9" }
 
 [dependencies.smoltcp]
 version = "0.6"
-features = ["ethernet", "proto-ipv4", "proto-ipv6", "socket-tcp"]
+features = ["ethernet", "proto-ipv4", "socket-tcp"]
 default-features = false

libboard_zynq/src/eth/rx.rs

@@ -2,6 +2,8 @@ use core::ops::Deref;
 use alloc::{vec, vec::Vec};
 use libcortex_a9::{asm::*, cache::*, UncachedSlice};
 use libregister::*;
+use log::debug;
+use crate::l2cache;
 use super::Buffer;
 
 #[derive(Debug)]
@@ -83,6 +85,7 @@ impl DescList {
             );
             // Flush buffer from cache, to be filled by the peripheral
             // before next read
+            l2cache().clean_invalidate_slice(&buffer[..]);
             dcci_slice(&buffer[..]);
         }
 
@@ -109,6 +112,8 @@ impl DescList {
             let word1 = entry.word1.read();
             let len = word1.frame_length_lsbs().into();
             let buffer = &mut self.buffers[self.next][0..len];
+            // l2cache().invalidate_slice(&mut buffer[..]);
+            // dcci_slice(&buffer[..]);
 
             self.next += 1;
             if self.next >= list_len {
@@ -117,8 +122,10 @@ impl DescList {
 
             let pkt = PktRef { entry, buffer };
             if word1.start_of_frame() && word1.end_of_frame() {
+                // debug!("pkt {}: {:08X}..{:08X}", len, &pkt.buffer[0] as *const _ as usize, &pkt.buffer[pkt.len()-1] as *const _ as usize);
                 Ok(Some(pkt))
             } else {
+                debug!("pkt trunc");
                 Err(Error::Truncated)
             }
         } else {
@@ -137,6 +144,7 @@ impl<'a> Drop for PktRef<'a> {
     fn drop(&mut self) {
         // Flush buffer from cache, to be filled by the peripheral
         // before next read
+        l2cache().invalidate_slice(self.buffer);
         dcci_slice(self.buffer);
 
         self.entry.word0.modify(|_, w| w.used(false));

libboard_zynq/src/eth/tx.rs

@@ -2,7 +2,8 @@ use core::ops::{Deref, DerefMut};
 use alloc::{vec, vec::Vec};
 use libcortex_a9::{cache::dcc_slice, UncachedSlice};
 use libregister::*;
-use log::warn;
+use log::{debug, warn};
+use crate::l2cache;
 use super::{Buffer, regs};
 
 /// Descriptor entry
@@ -95,8 +96,10 @@ impl DescList {
     }
 
     pub fn send<'s: 'p, 'p>(&'s mut self, regs: &'s mut regs::RegisterBlock, length: usize) -> Option<PktRef<'p>> {
+        // debug!("send {}", length);
         let list_len = self.list.len();
         let entry = &mut self.list[self.next];
+        // dmb();
         if entry.word1.read().used() {
             let buffer = &mut self.buffers[self.next][0..length];
             entry.word1.write(DescWord1::zeroed()
@@ -132,8 +135,12 @@ impl<'a> Drop for PktRef<'a> {
     fn drop(&mut self) {
         // Write back all dirty cachelines of this buffer
         dcc_slice(self.buffer);
+        l2cache().clean_slice(self.buffer);
 
         self.entry.word1.modify(|_, w| w.used(false));
+        // dcci(self.entry);
+        // l2cache().clean_invalidate(self.entry);
+        // dsb();
         if ! self.regs.tx_status.read().tx_go() {
             // Start TX if not already running
             self.regs.net_ctrl.modify(|_, w| w.start_tx(true));

libboard_zynq/src/lib.rs

@@ -34,8 +34,10 @@ pub fn setup_l2cache() {
         assert_eq!(&slcr.unnamed1 as *const _ as u32, 0xF8000A1C);
         unsafe { slcr.unnamed1.write(0x020202); }
     });
-
+    
     let mut l2 = l2cache();
+    use log::info;
+    info!("l2 aux={:08X}", l2.regs.aux_control.read());
     // TODO: set prefetch
 
     // Configure ZYNQ-specific latency

libcortex_a9/src/mmu.rs

@@ -158,7 +158,7 @@ impl L1Table {
                 global: true,
                 shareable: true,
                 access: AccessPermissions::FullAccess,
-                tex: 0b101,
+                tex: 0b111,
                 domain: 0b1111,
                 exec: true,
                 cacheable: true,