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libboard_zynq: fix pll_cp/pll_res swap in ClockSource::setup()

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Astro 2020-11-08 22:46:43 +01:00
parent 9ee77d8f44
commit 7e22010d7d
1 changed files with 1 additions and 1 deletions
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libboard_zynq/src/clocks/source.rs
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@ -57,7 +57,7 @@ pub trait ClockSource {
/// 25.10.4 PLLs /// 25.10.4 PLLs
fn setup(target_freq: u32) { fn setup(target_freq: u32) {
let fdiv = (target_freq / PS_CLK).min(66) as u16; let fdiv = (target_freq / PS_CLK).min(66) as u16;
let (pll_res, pll_cp, lock_cnt) = PLL_FDIV_LOCK_PARAM.iter() let (pll_cp, pll_res, lock_cnt) = PLL_FDIV_LOCK_PARAM.iter()
.filter(|(fdiv_max, _)| fdiv <= *fdiv_max) .filter(|(fdiv_max, _)| fdiv <= *fdiv_max)
.nth(0) .nth(0)
.expect("PLL_FDIV_LOCK_PARAM") .expect("PLL_FDIV_LOCK_PARAM")