forked from M-Labs/zynq-rs
eth: use UncachedSlice for both desc and buffers
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8267acfcba
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7c8ec46c8f
@ -59,7 +59,7 @@ register_bit!(desc_word1, global_broadcast, 31);
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#[repr(C)]
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#[repr(C)]
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pub struct DescList {
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pub struct DescList {
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list: UncachedSlice<DescEntry>,
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list: UncachedSlice<DescEntry>,
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buffers: Vec<Buffer>,
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buffers: UncachedSlice<Buffer>,
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next: usize,
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next: usize,
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}
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}
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@ -67,7 +67,8 @@ impl DescList {
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pub fn new(size: usize) -> Self {
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pub fn new(size: usize) -> Self {
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let mut list = UncachedSlice::new(size, || DescEntry::zeroed())
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let mut list = UncachedSlice::new(size, || DescEntry::zeroed())
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.unwrap();
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.unwrap();
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let mut buffers = vec![Buffer::new(); size];
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let mut buffers = UncachedSlice::new(size, || Buffer::new())
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.unwrap();
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let last = list.len().min(buffers.len()) - 1;
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let last = list.len().min(buffers.len()) - 1;
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for (i, (entry, buffer)) in list.iter_mut().zip(buffers.iter_mut()).enumerate() {
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for (i, (entry, buffer)) in list.iter_mut().zip(buffers.iter_mut()).enumerate() {
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@ -83,8 +84,8 @@ impl DescList {
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entry.word1.write(
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entry.word1.write(
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DescWord1::zeroed()
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DescWord1::zeroed()
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);
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);
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l2cache().invalidate_slice(&mut buffer[..]);
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// l2cache().invalidate_slice(&mut buffer[..]);
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dcci_slice(&buffer[..]);
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// dcci_slice(&buffer[..]);
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}
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}
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DescList {
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DescList {
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@ -141,10 +142,10 @@ pub struct PktRef<'a> {
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impl<'a> Drop for PktRef<'a> {
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impl<'a> Drop for PktRef<'a> {
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fn drop(&mut self) {
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fn drop(&mut self) {
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// Flush buffer from cache, to be filled by the peripheral
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// // Flush buffer from cache, to be filled by the peripheral
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// before next read
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// // before next read
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l2cache().invalidate_slice(self.buffer);
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// l2cache().invalidate_slice(self.buffer);
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dcci_slice(self.buffer);
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// dcci_slice(self.buffer);
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self.entry.word0.modify(|_, w| w.used(false));
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self.entry.word0.modify(|_, w| w.used(false));
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dmb();
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dmb();
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@ -1,6 +1,7 @@
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use core::ops::{Deref, DerefMut};
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use core::ops::{Deref, DerefMut};
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use alloc::{vec, vec::Vec};
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use alloc::{vec, vec::Vec};
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use libcortex_a9::{asm::dmb, cache::dcc_slice, UncachedSlice};
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use libcortex_a9::{asm::dmb, cache::dcc_slice, UncachedSlice};
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//use libcortex_a9::{asm::*, cache::*, UncachedSlice};
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use libregister::*;
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use libregister::*;
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use log::{debug, warn};
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use log::{debug, warn};
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use crate::l2cache;
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use crate::l2cache;
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@ -46,7 +47,7 @@ pub const DESCS: usize = 8;
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#[repr(C)]
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#[repr(C)]
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pub struct DescList {
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pub struct DescList {
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list: UncachedSlice<DescEntry>,
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list: UncachedSlice<DescEntry>,
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buffers: Vec<Buffer>,
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buffers: UncachedSlice<Buffer>,
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next: usize,
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next: usize,
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}
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}
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@ -54,7 +55,8 @@ impl DescList {
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pub fn new(size: usize) -> Self {
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pub fn new(size: usize) -> Self {
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let mut list = UncachedSlice::new(size, || DescEntry::zeroed())
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let mut list = UncachedSlice::new(size, || DescEntry::zeroed())
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.unwrap();
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.unwrap();
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let mut buffers = vec![Buffer::new(); size];
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let mut buffers = UncachedSlice::new(size, || Buffer::new())
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.unwrap();
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let last = list.len().min(buffers.len()) - 1;
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let last = list.len().min(buffers.len()) - 1;
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// Sending seems to not work properly with only one packet
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// Sending seems to not work properly with only one packet
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@ -133,9 +135,9 @@ pub struct PktRef<'a> {
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impl<'a> Drop for PktRef<'a> {
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impl<'a> Drop for PktRef<'a> {
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fn drop(&mut self) {
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fn drop(&mut self) {
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// Write back all dirty cachelines of packet buffer
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// // Write back all dirty cachelines of packet buffer
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dcc_slice(self.buffer);
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// dcc_slice(self.buffer);
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l2cache().clean_slice(self.buffer);
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// l2cache().clean_slice(self.buffer);
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self.entry.word1.modify(|_, w| w.used(false));
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self.entry.word1.modify(|_, w| w.used(false));
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dmb();
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dmb();
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