forked from M-Labs/zynq-rs
eth: fix cache maintenance
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7f3e75e20c
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7ae8be58cf
@ -217,7 +217,7 @@ if false {
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while let Ok(stream) = TcpStream::accept(TCP_PORT, 0x10_0000, 0x10_0000).await {
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let stats_tx = stats_tx.clone();
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task::spawn(async move {
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let tx_data = (0..=255).take(4096).collect::<alloc::vec::Vec<u8>>();
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let tx_data = (0..=255).take(65536).collect::<alloc::vec::Vec<u8>>();
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loop {
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// const CHUNK_SIZE: usize = 65536;
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// match stream.send((0..=255).cycle().take(CHUNK_SIZE)).await {
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@ -83,10 +83,6 @@ impl DescList {
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entry.word1.write(
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DescWord1::zeroed()
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);
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// Flush buffer from cache, to be filled by the peripheral
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// before next read
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l2cache().clean_invalidate_slice(&buffer[..]);
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dcci_slice(&buffer[..]);
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}
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DescList {
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@ -112,8 +108,9 @@ impl DescList {
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let word1 = entry.word1.read();
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let len = word1.frame_length_lsbs().into();
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let buffer = &mut self.buffers[self.next][0..len];
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// l2cache().invalidate_slice(&mut buffer[..]);
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// dcci_slice(&buffer[..]);
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// Invalidate caches for packet buffer
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l2cache().invalidate_slice(&mut buffer[..]);
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dcci_slice(&buffer[..]);
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self.next += 1;
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if self.next >= list_len {
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@ -142,10 +139,6 @@ pub struct PktRef<'a> {
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impl<'a> Drop for PktRef<'a> {
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fn drop(&mut self) {
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// Flush buffer from cache, to be filled by the peripheral
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// before next read
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l2cache().invalidate_slice(self.buffer);
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dcci_slice(self.buffer);
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self.entry.word0.modify(|_, w| w.used(false));
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dmb();
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@ -1,6 +1,6 @@
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use core::ops::{Deref, DerefMut};
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use alloc::{vec, vec::Vec};
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use libcortex_a9::{cache::dcc_slice, UncachedSlice};
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use libcortex_a9::{asm::dmb, cache::dcc_slice, UncachedSlice};
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use libregister::*;
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use log::{debug, warn};
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use crate::l2cache;
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@ -99,7 +99,7 @@ impl DescList {
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// debug!("send {}", length);
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let list_len = self.list.len();
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let entry = &mut self.list[self.next];
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// dmb();
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dmb();
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if entry.word1.read().used() {
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let buffer = &mut self.buffers[self.next][0..length];
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entry.word1.write(DescWord1::zeroed()
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@ -133,13 +133,12 @@ pub struct PktRef<'a> {
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impl<'a> Drop for PktRef<'a> {
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fn drop(&mut self) {
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// Write back all dirty cachelines of this buffer
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// Write back all dirty cachelines of packet buffer
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dcc_slice(self.buffer);
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l2cache().clean_slice(self.buffer);
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self.entry.word1.modify(|_, w| w.used(false));
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// dcci(self.entry);
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// l2cache().clean_invalidate(self.entry);
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dmb();
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// dsb();
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if ! self.regs.tx_status.read().tx_go() {
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// Start TX if not already running
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