zynq::flash: begin driver implementation

This commit is contained in:
Astro 2019-11-21 00:14:09 +01:00
parent 8037042040
commit 3180f1c3f7
4 changed files with 157 additions and 2 deletions

67
src/zynq/flash/mod.rs Normal file
View File

@ -0,0 +1,67 @@
//! Quad-SPI Flash Controller
use crate::regs::{RegisterW, RegisterRW};
use super::slcr;
use super::clocks::CpuClocks;
pub mod regs;
/// Flash Interface Driver
pub struct Flash {
regs: &'static mut regs::RegisterBlock,
}
impl Flash {
pub fn new(clock: u32) -> Self {
Self::enable_clocks(clock);
Self::setup_signals();
Self::reset();
let regs = regs::RegisterBlock::qspi();
let mut flash = Flash { regs };
flash.configure();
flash
}
fn enable_clocks(clock: u32) {
let io_pll = CpuClocks::get().io;
let divisor = ((clock - 1 + io_pll) / clock)
.max(1).min(63) as u8;
slcr::RegisterBlock::unlocked(|slcr| {
slcr.lqspi_clk_ctrl.write(
slcr::LqspiClkCtrl::zeroed()
.src_sel(slcr::PllSource::IoPll)
.divisor(divisor)
.clkact(true)
);
});
}
fn setup_signals() {
// TODO
}
fn reset() {
slcr::RegisterBlock::unlocked(|slcr| {
slcr.lqspi_rst_ctrl.write(
slcr::LqspiRstCtrl::zeroed()
.ref_rst(true)
.cpu1x_rst(true)
);
slcr.lqspi_rst_ctrl.write(
slcr::LqspiRstCtrl::zeroed()
);
});
}
fn configure(&mut self) {
self.regs.config.modify(|_, w| w
.baud_rate_div(4 /* TODO */)
.mode_sel(true)
.leg_flsh(true)
.endian(false)
.fifo_width(0b11)
);
}
}

78
src/zynq/flash/regs.rs Normal file
View File

@ -0,0 +1,78 @@
use volatile_register::{RO, WO, RW};
use crate::{register, register_bit, register_bits, register_bits_typed};
#[repr(C)]
pub struct RegisterBlock {
pub config: Config,
pub intr_status: RW<u32>,
pub intr_en: RW<u32>,
pub intr_dis: RW<u32>,
pub intr_mask: RO<u32>,
pub enable: RW<u32>,
pub delay: RW<u32>,
pub txd0: WO<u32>,
pub rx_data: RO<u32>,
pub slave_idle_count: RW<u32>,
pub tx_thres: RW<u32>,
pub rx_thes: RW<u32>,
pub gpio: RW<u32>,
pub _unused1: RO<u32>,
pub lpbk_dly_adj: RW<u32>,
pub _unused2: [RO<u32>; 17],
pub txd1: WO<u32>,
pub txd2: WO<u32>,
pub txd3: WO<u32>,
pub _unused3: [RO<u32>; 5],
pub lqspi_cfg: RW<u32>,
pub lqspi_sts: RW<u32>,
pub _unused4: [RO<u32>; 21],
pub mod_id: RW<u32>,
}
impl RegisterBlock {
const BASE_ADDRESS: *mut Self = 0xE000D000 as *mut _;
pub fn qspi() -> &'static mut Self {
unsafe { &mut *Self::BASE_ADDRESS }
}
}
register!(config, Config, RW, u32);
register_bit!(config,
/// Enables master mode
mode_sel, 0);
register_bit!(config,
/// Clock polarity low/high
clk_pol, 1);
register_bit!(config,
/// Clock phase
clk_ph, 2);
register_bits!(config,
/// divisor = 2 ** (1 + baud_rate_div)
baud_rate_div, u8, 3, 5);
register_bits!(config,
/// Must be set to 0b11
fifo_width, u8, 6, 7);
register_bit!(config,
/// Must be 0
ref_clk, 8);
register_bit!(config,
/// Peripheral Chip Select Line
pcs, 10);
register_bit!(config,
/// false: auto mode, true: manual CS mode
manual_cs, 14);
register_bit!(config,
/// false: auto mode, true: enables manual start enable
man_start_en, 15);
register_bit!(config,
/// false: auto mode, true: enables manual start command
man_start_com, 16);
register_bit!(config, holdb_dr, 19);
register_bit!(config,
/// false: little, true: endian
endian, 26);
register_bit!(config,
/// false: legacy SPI mode, true: Flash memory interface mode
leg_flsh, 31);

View File

@ -6,3 +6,4 @@ pub mod axi_hp;
pub mod axi_gp; pub mod axi_gp;
pub mod ddr; pub mod ddr;
pub mod mpcore; pub mod mpcore;
pub mod flash;

View File

@ -84,7 +84,7 @@ pub struct RegisterBlock {
pub gem0_clk_ctrl: GemClkCtrl, pub gem0_clk_ctrl: GemClkCtrl,
pub gem1_clk_ctrl: GemClkCtrl, pub gem1_clk_ctrl: GemClkCtrl,
pub smc_clk_ctrl: RW<u32>, pub smc_clk_ctrl: RW<u32>,
pub lqspi_clk_ctrl: RW<u32>, pub lqspi_clk_ctrl: LqspiClkCtrl,
pub sdio_clk_ctrl: RW<u32>, pub sdio_clk_ctrl: RW<u32>,
pub uart_clk_ctrl: UartClkCtrl, pub uart_clk_ctrl: UartClkCtrl,
pub spi_clk_ctrl: RW<u32>, pub spi_clk_ctrl: RW<u32>,
@ -124,7 +124,7 @@ pub struct RegisterBlock {
pub i2c_rst_ctrl: RW<u32>, pub i2c_rst_ctrl: RW<u32>,
pub uart_rst_ctrl: UartRstCtrl, pub uart_rst_ctrl: UartRstCtrl,
pub gpio_rst_ctrl: RW<u32>, pub gpio_rst_ctrl: RW<u32>,
pub lqspi_rst_ctrl: RW<u32>, pub lqspi_rst_ctrl: LqspiRstCtrl,
pub smc_rst_ctrl: RW<u32>, pub smc_rst_ctrl: RW<u32>,
pub ocm_rst_ctrl: RW<u32>, pub ocm_rst_ctrl: RW<u32>,
reserved4: [u32; 1], reserved4: [u32; 1],
@ -440,6 +440,15 @@ impl UartRstCtrl {
} }
} }
register!(lqspi_clk_ctrl, LqspiClkCtrl, RW, u32);
register_bit!(lqspi_clk_ctrl, clkact, 0);
register_bits_typed!(lqspi_clk_ctrl, src_sel, u8, PllSource, 4, 5);
register_bits!(lqspi_clk_ctrl, divisor, u8, 8, 13);
register!(lqspi_rst_ctrl, LqspiRstCtrl, RW, u32);
register_bit!(lqspi_rst_ctrl, ref_rst, 1);
register_bit!(lqspi_rst_ctrl, cpu1x_rst, 0);
register!(a9_cpu_rst_ctrl, A9CpuRstCtrl, RW, u32); register!(a9_cpu_rst_ctrl, A9CpuRstCtrl, RW, u32);
register_bit!(a9_cpu_rst_ctrl, peri_rst, 8); register_bit!(a9_cpu_rst_ctrl, peri_rst, 8);
register_bit!(a9_cpu_rst_ctrl, a9_clkstop1, 5); register_bit!(a9_cpu_rst_ctrl, a9_clkstop1, 5);