forked from M-Labs/zynq-rs
main: just test for qspi flash
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@ -1,34 +1,16 @@
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#![no_std]
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#![no_main]
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use core::mem::transmute;
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use libcortex_a9::mutex::Mutex;
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use libboard_zynq::{print, println, self as zynq, clocks::Clocks, clocks::source::{ClockSource, ArmPll, IoPll}};
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use libsupport_zynq::{
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ram, alloc::{vec, vec::Vec},
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boot,
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smoltcp::wire::{EthernetAddress, IpAddress, IpCidr},
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smoltcp::iface::{NeighborCache, EthernetInterfaceBuilder},
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smoltcp::time::Instant,
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smoltcp::socket::SocketSet,
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smoltcp::socket::{TcpSocket, TcpSocketBuffer},
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};
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const HWADDR: [u8; 6] = [0, 0x23, 0xde, 0xea, 0xbe, 0xef];
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static mut STACK_CORE1: [u32; 512] = [0; 512];
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use libsupport_zynq as _;
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#[no_mangle]
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pub fn main_core0() {
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// zynq::clocks::Clocks::enable_io(1_250_000_000);
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println!("\nzc706 main");
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let clocks = zynq::clocks::Clocks::get();
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println!("CPU Clocks: {}/{}/{}/{}", clocks.cpu_6x4x(), clocks.cpu_3x2x(), clocks.cpu_2x(), clocks.cpu_1x());
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{
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use libregister::RegisterR;
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println!("Boot mode: {:?}", zynq::slcr::RegisterBlock::new().boot_mode.read().boot_mode_pins());
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}
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// Clock setup
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#[cfg(feature = "target_zc706")]
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const CPU_FREQ: u32 = 800_000_000;
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#[cfg(feature = "target_cora_z7_10")]
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@ -43,6 +25,7 @@ pub fn main_core0() {
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let clocks = zynq::clocks::Clocks::get();
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println!("CPU Clocks: {}/{}/{}/{}", clocks.cpu_6x4x(), clocks.cpu_3x2x(), clocks.cpu_2x(), clocks.cpu_1x());
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// Flash: Linear Addressing Mode
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let mut flash = zynq::flash::Flash::new(200_000_000).linear_addressing_mode();
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let flash_ram: &[u8] = unsafe { core::slice::from_raw_parts(flash.ptr(), flash.size()) };
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for i in 0..=1 {
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@ -54,26 +37,10 @@ pub fn main_core0() {
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}
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let mut flash = flash.stop();
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for i in 0../*=*/1 {
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// Flash: Manual I/O Mode
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for i in 0..=1 {
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let mut flash_io = flash.manual_mode(i);
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let mut cr: zynq::flash::CR = flash_io.read_reg();
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println!("rdcr={:02X}", cr.inner);
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// if cr.quad() {
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// println!("disabling quad mode...");
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// cr.set_quad(false);
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// let sr1: zynq::flash::SR1 = flash_io.read_reg();
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// println!("sr1={:02X}", sr1.inner);
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// flash_io.write_regs(sr1, cr);
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// }
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// if ! cr.quad() {
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// println!("setting quad mode...");
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// cr.set_quad(true);
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// let sr1: zynq::flash::SR1 = flash_io.read_reg();
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// // println!("sr1={:02X}", sr1.inner);
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// flash_io.write_regs(sr1, cr);
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// }
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print!("Flash {} ID:", i);
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for (i, b) in flash_io.rdid().enumerate() {
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print!(" {:02X}", b);
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@ -108,15 +75,13 @@ pub fn main_core0() {
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for o in 0..8 {
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const SIZE: u32 = 0x100;
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println!("WREN");
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flash_io.write_enabled(|flash_io| {
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println!("Erase page {}", o);
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flash_io.erase(o * SIZE);
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});
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println!("WREN");
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flash_io.write_enabled(|flash_io| {
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println!("Program page {}", o);
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flash_io.program(o * SIZE, [0x26121984; (SIZE >> 2) as usize].iter().cloned());
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flash_io.program(o * SIZE, [0x55FD02AA; (SIZE >> 2) as usize].iter().cloned());
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});
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}
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@ -131,134 +96,9 @@ pub fn main_core0() {
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flash = flash_io.stop();
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}
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let core1_stack = unsafe { &mut STACK_CORE1[..] };
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println!("{} bytes stack for core1", core1_stack.len());
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let core1 = boot::Core1::start(core1_stack);
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for _ in 0..0x1000000 {
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let mut l = SHARED.lock();
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*l += 1;
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}
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while !*DONE.lock() {
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let x = { *SHARED.lock() };
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println!("shared: {:08X}", x);
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}
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let x = { *SHARED.lock() };
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println!("done shared: {:08X}", x);
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core1.reset();
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libcortex_a9::asm::dsb();
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print!("Core1 stack [{:08X}..{:08X}]:", &core1.stack[0] as *const _ as u32, &core1.stack[core1.stack.len() - 1] as *const _ as u32);
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for w in core1.stack {
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print!(" {:08X}", w);
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}
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println!(".");
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let mut ddr = zynq::ddr::DdrRam::new();
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// #[cfg(not(feature = "target_zc706"))]
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ddr.memtest();
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ram::init_alloc(&mut ddr);
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let eth = zynq::eth::Eth::default(HWADDR.clone());
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println!("Eth on");
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const RX_LEN: usize = 8;
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let mut rx_descs = (0..RX_LEN)
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.map(|_| zynq::eth::rx::DescEntry::zeroed())
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.collect::<Vec<_>>();
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let mut rx_buffers = vec![[0u8; zynq::eth::MTU]; RX_LEN];
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// Number of transmission buffers (minimum is two because with
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// one, duplicate packet transmission occurs)
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const TX_LEN: usize = 8;
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let mut tx_descs = (0..TX_LEN)
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.map(|_| zynq::eth::tx::DescEntry::zeroed())
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.collect::<Vec<_>>();
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let mut tx_buffers = vec![[0u8; zynq::eth::MTU]; TX_LEN];
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let eth = eth.start_rx(&mut rx_descs, &mut rx_buffers);
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//let mut eth = eth.start_tx(&mut tx_descs, &mut tx_buffers);
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let mut eth = eth.start_tx(
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// HACK
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unsafe { transmute(tx_descs.as_mut_slice()) },
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unsafe { transmute(tx_buffers.as_mut_slice()) },
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);
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let ethernet_addr = EthernetAddress(HWADDR);
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// IP stack
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let local_addr = IpAddress::v4(192, 168, 1, 51);
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let mut ip_addrs = [IpCidr::new(local_addr, 24)];
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let mut neighbor_storage = vec![None; 256];
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let neighbor_cache = NeighborCache::new(&mut neighbor_storage[..]);
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let mut iface = EthernetInterfaceBuilder::new(&mut eth)
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.ethernet_addr(ethernet_addr)
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.ip_addrs(&mut ip_addrs[..])
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.neighbor_cache(neighbor_cache)
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.finalize();
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let mut sockets_storage = [
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None, None, None, None,
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None, None, None, None
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];
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let mut sockets = SocketSet::new(&mut sockets_storage[..]);
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// taken from example code for smoltcp
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let mut tcp_server_rx_data = vec![0; 512 * 1024];
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let mut tcp_server_tx_data = vec![0; 512 * 1024];
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let tcp_rx_buffer = TcpSocketBuffer::new(&mut tcp_server_rx_data[..]);
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let tcp_tx_buffer = TcpSocketBuffer::new(&mut tcp_server_tx_data[..]);
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let tcp_socket = TcpSocket::new(tcp_rx_buffer, tcp_tx_buffer);
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let tcp_handle = sockets.add(tcp_socket);
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/// `chargen`
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const TCP_PORT: u16 = 19;
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let mut time = 0u32;
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loop {
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time += 1;
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let timestamp = Instant::from_millis(time);
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match iface.poll(&mut sockets, timestamp) {
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Ok(_) => {},
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Err(e) => {
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println!("poll error: {}", e);
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}
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}
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// (mostly) taken from smoltcp example: TCP echo server
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let mut socket = sockets.get::<TcpSocket>(tcp_handle);
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if !socket.is_open() {
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socket.listen(TCP_PORT).unwrap()
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}
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if socket.may_recv() && socket.can_send() {
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socket.recv(|buf| {
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let len = buf.len().min(4096);
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let buffer = buf[..len].iter().cloned().collect::<Vec<_>>();
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(len, buffer)
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})
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.and_then(|buffer| socket.send_slice(&buffer[..]))
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.map(|_| {})
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.unwrap_or_else(|e| println!("tcp: {:?}", e));
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}
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}
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// #[allow(unreachable_code)]
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// drop(tx_descs);
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// #[allow(unreachable_code)]
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// drop(tx_buffers);
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}
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static SHARED: Mutex<u32> = Mutex::new(0);
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static DONE: Mutex<bool> = Mutex::new(false);
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#[no_mangle]
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pub fn main_core1() {
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println!("Hello from core1!");
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for _ in 0..0x1000000 {
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let mut l = SHARED.lock();
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*l += 1;
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}
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println!("core1 done!");
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*DONE.lock() = true;
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loop {}
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}
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@ -388,7 +388,7 @@ impl Flash<Manual> {
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sr1.inner,
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cr.inner,
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];
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flash.transfer(args.into_iter().cloned(), 3);
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flash.transfer(args.iter().cloned(), 3);
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});
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}
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@ -1,7 +1,5 @@
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use libregister::{RegisterR, RegisterW, RegisterRW};
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use super::regs;
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use libregister::{RegisterR, RegisterRW};
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use super::{SpiWord, Flash, Manual};
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use crate::{print, println};
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pub struct Transfer<'a, Args: Iterator<Item = W>, W: Into<SpiWord>> {
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flash: &'a mut Flash<Manual>,
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@ -114,7 +112,7 @@ impl<'a, Args: Iterator<Item = W>, W: Into<SpiWord>> Drop for Transfer<'a, Args,
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.man_start_com(false)
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);
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/// Leave PCS high for a few cycles
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// Leave PCS high for a few cycles
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for _ in 0..0x100 {
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libcortex_a9::asm::nop();
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}
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