forked from M-Labs/zynq-rs
add static exception handling
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parent
b13bf72c17
commit
2df74cc055
14
link.x
14
link.x
@ -1,6 +1,14 @@
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ENTRY(_boot_cores);
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STACK_SIZE = 0x2000 - 0x10;
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PROVIDE(Reset = _boot_cores);
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PROVIDE(UndefinedInstruction = Reset);
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PROVIDE(SoftwareInterrupt = Reset);
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PROVIDE(PrefetchAbort = Reset);
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PROVIDE(DataAbort = Reset);
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PROVIDE(ReservedException = Reset);
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PROVIDE(IRQ = Reset);
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PROVIDE(FIQ = Reset);
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MEMORY
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{
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@ -10,9 +18,13 @@ MEMORY
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SECTIONS
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{
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.exceptions :
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{
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. = 0x0;
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KEEP(*(.text.exceptions));
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} > OCM
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.text :
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{
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/* Starts at LOADER_ADDR. */
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. = 0x8000;
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KEEP(*(.text.boot))
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*(.text .text.*)
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12
src/cortex_a9/exceptions.s
Normal file
12
src/cortex_a9/exceptions.s
Normal file
@ -0,0 +1,12 @@
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.section ".text.exceptions"
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.global exception_vector
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exception_vector:
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b Reset
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b UndefinedInstruction
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b SoftwareInterrupt
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b PrefetchAbort
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b DataAbort
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b ReservedException
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b IRQ
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b FIQ
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@ -1,2 +1,4 @@
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pub mod asm;
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pub mod regs;
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global_asm!(include_str!("exceptions.s"));
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11
src/main.rs
11
src/main.rs
@ -1,6 +1,7 @@
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#![no_std]
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#![no_main]
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#![feature(asm)]
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#![feature(global_asm)]
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#![feature(naked_functions)]
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use core::fmt::Write;
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@ -94,3 +95,13 @@ fn panic(info: &core::panic::PanicInfo) -> ! {
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slcr::RegisterBlock::unlocked(|slcr| slcr.soft_reset());
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unreachable!()
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}
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#[no_mangle]
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pub unsafe extern "C" fn PrefetchAbort() {
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panic!("PrefetchAbort");
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}
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#[no_mangle]
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pub unsafe extern "C" fn DataAbort() {
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panic!("DataAbort");
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}
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