astro/zynq-rs
1
0
Fork 0
forked from M-Labs/zynq-rs
Code Issues Pull Requests Releases Wiki Activity

mpidr: wrap with proper bitfield getters

Browse Source 
Prevents callers from dealing with CORE_MASK.
This commit is contained in:
Astro 2020-07-07 23:51:33 +02:00
parent 371e59cef5
commit 191abf6b8f
3 changed files with 14 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
libcortex_a9/src/regs.rs
View File

@ -91,8 +91,19 @@ pub struct HVBAR;
def_reg_r!(HVBAR, u32, "mrc p15, 4, $0, c12, c0, 0"); def_reg_r!(HVBAR, u32, "mrc p15, 4, $0, c12, c0, 0");
def_reg_w!(HVBAR, u32, "mcr p15, 4, $0, c12, c0, 0"); def_reg_w!(HVBAR, u32, "mcr p15, 4, $0, c12, c0, 0");
/// Multiprocess Affinity Register
pub struct MPIDR; pub struct MPIDR;
def_reg_r!(MPIDR, u32, "mrc p15, 0, $0, c0, c0, 5"); def_reg_r!(MPIDR, mpidr::Read, "mrc p15, 0, $0, c0, c0, 5");
wrap_reg!(mpidr);
register_bits!(mpidr,
/// CPU core index
cpu_id, u8, 0, 1);
register_bits!(mpidr,
/// Processor index in "multi-socket" systems
cluster_id, u8, 8, 11);
register_bit!(mpidr,
/// true if part of uniprocessor system
u, 30);
pub struct DFAR; pub struct DFAR;
def_reg_r!(DFAR, u32, "mrc p15, 0, $0, c6, c0, 0"); def_reg_r!(DFAR, u32, "mrc p15, 0, $0, c6, c0, 0");

3
libsupport_zynq/src/abort.rs
View File

@ -35,8 +35,7 @@ pub unsafe extern "C" fn PrefetchAbort() {
pub unsafe extern "C" fn DataAbort() { pub unsafe extern "C" fn DataAbort() {
stdio::drop_uart(); stdio::drop_uart();
const CORE_MASK: u32 = 0x3; println!("DataAbort on core {}", MPIDR.read().cpu_id());
println!("DataAbort on core {}", MPIDR.read() & CORE_MASK);
println!("DFSR: {:03X}", DFSR.read()); println!("DFSR: {:03X}", DFSR.read());
loop {} loop {}

4
libsupport_zynq/src/boot.rs
View File

@ -22,9 +22,7 @@ static mut CORE1_ENABLED: VolatileCell<bool> = VolatileCell::new(false);
#[no_mangle] #[no_mangle]
#[naked] #[naked]
pub unsafe extern "C" fn Reset() -> ! { pub unsafe extern "C" fn Reset() -> ! {
const CORE_MASK: u32 = 0x3; match MPIDR.read().cpu_id() {
match MPIDR.read() & CORE_MASK {
0 => { 0 => {
SP.write(&mut __stack0_start as *mut _ as u32); SP.write(&mut __stack0_start as *mut _ as u32);
boot_core0(); boot_core0();